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ADDR7 Scheda tecnica(PDF) 6 Page - List of Unclassifed Manufacturers |
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ADDR7 Scheda tecnica(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 68 page Key Fe ature s 2 NS 75 20 Da ta shee t 03 /2 00 6 Key Features This table lists the key features of the NS7520. CPU core Integrated 10/100 Ethernet MAC ARM7TDMI 32-bit RISC processor 32-bit internal bus 32-bit ARM and 16-bit Thumb mode 15 general purpose 32-bit registers 32-bit program counter (PC) and status register Five supervisor modes, one user mode 10/100 Mbps MII-based PHY interface 10 Mbps ENDEC interface TP-PMD and fiber-PMD device support Full-duplex and half-duplex modes Optional 4B/5B coding Station, broadcast, and multicast address detection 512-byte transmit FIFO, 2 Kbyte receive FIFO Intelligent receive-side buffer selection 13-Channel DMA controller Programmable Timers Two channels dedicated to Ethernet transmit and receive Four channels dedicated to two serial modules’ transmit and receive Four channels for external peripherals. Only two channels — either 3 and 5 or 4 and 6 — can be configured at one time. Three channels available for memory-to-memory transfers Flexible buffer management Two independent timers (2μs–20.7 hours) Watchdog timer (interrupt or reset on expiration) Programmable bus monitor or timer General purpose I/O pins Operating frequency 16 programmable GPIO interface pins 4 pins programmable with level-sensitive interrupt 36, 46, or 55 MHz internal clock operation from 18.432 MHz crystal fMAX = 36, 46, or 55 (grade–dependent) System clock source by external quartz crystal or crystal oscillator, or clock signal Programmable PLL, which allows a range of operating frequencies from 10 to fMAX Maximum operating frequency from external clock or using PLL multiplication fMAX |
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