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MC-4R512FKK8K-840 Scheda tecnica(PDF) 9 Page - Elpida Memory

Il numero della parte MC-4R512FKK8K-840
Spiegazioni elettronici  512MB 32-bit Direct Rambus DRAM RIMM Module
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Produttore elettronici  ELPIDA [Elpida Memory]
Homepage  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

MC-4R512FKK8K-840 Scheda tecnica(HTML) 9 Page - Elpida Memory

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MC-4R512FKK8K
Preliminary Data Sheet E0254N10 (Ver. 1.0)
9
AC Electrical Specifications
Symbol
Parameter and Conditions
Note1
MIN.
TYP.
MAX.
Unit
ZL
Module Impedance of RSL signals
25.2
28.0
30.8
ZUL
−CMOS
Module Impedance of SCK and CMD signals
23.8
28.0
32.2
TPD
Average clock delay from finger to finger of all RSL clock
nets (CTM, CTMN,CFM, and CFMN)
Note2
1.36
ns
∆TPD
Propagation delay variation of RSL signals with respect to
TPD
Note1, 3
−21
+21
ps
∆TPD-CMOS
Propagation delay variation of SCK signal with respect to
an average clock delay
Note1
−250
+250
ps
∆TPD- SCK,CMD
Propagation delay variation of CMD signal with respect to
SCK signal
−200
+200
ps
V
α/VIN
Attenuation Limit
16.0
%
VXF/VIN
Forward crosstalk coefficient
(300ps input rise time 20% - 80%)
4.0
%
VXB/VIN
Backward crosstalk coefficient
(300ps input rise time 20% - 80%)
2.0
%
RDC
DC Resistance Limit
0.8
Notes 1. Specifications apply per channel.
2. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets
(CTM, CTMN, CFM, and CFMN).
3. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted
∆TPD Specification” table.
Adjusted
∆∆∆∆TPD Specification
Absolute
Symbol
Parameter and conditions
Adjusted MIN./MAX.
MIN.
MAX.
Unit
∆TPD
Propagation delay variation of RSL signals with
respect to TPD
+/
− [17+(18*N*∆Z0)] Note
−30
30
ps
Note
N = Number of RDRAM devices installed on the RIMM module.
∆Z0 = delta Z0% = (MAX. Z0 - MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)


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