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MC-4R128FKE8S-845 Scheda tecnica(PDF) 9 Page - Elpida Memory |
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MC-4R128FKE8S-845 Scheda tecnica(HTML) 9 Page - Elpida Memory |
9 / 14 page Data Sheet E0139N30 (Ver. 3.0) 9 MC-4R128FKE8S AC Electrical Specifications Symbol Parameter and Conditions MIN. TYP. MAX. Unit Z Module Impedance of RSL signals 25.2 28.0 30.8 Ω Module Impedance of SCK and CMD signals 23.8 28.0 32.2 TPD Average clock delay from finger to finger of all RSL clock nets 1.06 ns (CTM, CTMN,CFM, and CFMN) ∆TPD Propagation delay variation of RSL signals with respect to TPD Note1,2 -21 +21 ps ∆TPD-CMOS Propagation delay variation of SCK signal with respect to an average clock delay Note1 -250 +250 ps ∆TPD- SCK,CMD Propagation delay variation of CMD signal with respect to SCK signal -200 +200 ps Vα/VIN Attenuation Limit -845 12.0 % VXF/VIN Forward crosstalk coefficient -845 2.0 % VXB/VIN Backward crosstalk coefficient -845 1.5 % RDC DC Resistance Limit -845 0.9 Ω Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN). 2. If the SO-RIMM module meets the following specification, then it is compliant to the specification. If the SO-RIMM module does not meet these specifications, then the specification can be adjusted by the “Adjusted ∆TPD Specification” table. Adjusted ∆∆∆∆TPD Specification Symbol Parameter and conditions Adjusted MIN./MAX. Absolute Unit MIN. MAX. ∆TPD Propagation delay variation of RSL signals with respect to TPD +/ − [17+(18*N*∆Z0)] Note -30 +30 ps Note N = Number of RDRAM devices installed on the SO-RIMM module. ∆Z0 = delta Z0% = (MAX. Z0 − MIN. Z0) / (MIN. Z0) (MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the module.) |
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