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BU16501KS2-E2 Scheda tecnica(PDF) 6 Page - Rohm |
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BU16501KS2-E2 Scheda tecnica(HTML) 6 Page - Rohm |
6 / 32 page 6/29 Datasheet Datasheet BU16501KS2 © 2013 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 TSZ02201-0G3G0CZ00250-1-2 01.Oct.2013 Rev.001 Electrical Characteristics - continued Parameter Symbol Limit Unit Condition Min Typ Max [ SDA, SCL ] L level input voltage VIL2 -0.3 - 0.25×VIO V H level input voltage VIH2 0.75×VIO - VIO+0.3 V Input hysteresis Vhys 0.05×VIO - - V L level output voltage (for SDA pin) VOL2 - - 0.3 V IOL=3mA Input current Iin2 -3 - 3 μA Input voltage = from (0.1 x VIO) to (0.9 x VIO) [ RESETB ] L level input voltage VIL3 -0.3 - 0.25×VIO V H level input voltage VIH3 0.75×VIO - VIO+0.3 V Input current Iin3 - 0 1 μA Input voltage = from (0.1 x VIO) to (0.9 x VIO) 【CLKIO(output)】 L level output voltage VOL1 - - 0.4 V IOL=2mA H level output voltage VOH1 VIO-0.4 - - V IOH=-2mA 【CLKIO(input)】 L level input voltage VIL4 -0.3 - 0.25×VIO V H level input voltage VIH4 0.75×VIO - VIO+0.3 V Input current Iin4 - 10 20 μA Input voltage =5.0V (Unless otherwise specified, Ta=25°C, VBAT=5.0V, VINSW=5.0V, VIO=5.0V) Parameter Symbol Limit Unit Condition Min Typ Max SCL cycle time tscyc 76 - - ns H period of SCL cycle Twhc 35 - - ns L period of SCL cycle Twlc 35 - - ns SDA setup time Tss 38 - - ns SDA hold time Tsh 38 - - ns Write interval Tcsw 38 - - ns Write interval (after RAM accsess) 2.1 - - μs (Note 1) ECLK x 2 - - s (Note 2) CE setup time Tcss 55 - - ns CE hold time Tcgh 48 - - ns (Note 1) When it used internal clock. (Note 2) When it used external clock. (ECLK means the cycle of external clock) (Unless otherwise specified, Ta=25 oC, VBAT=5.0V, VINSW=5.0V, VIO=5.0V) Parameter Symbol Standard-mode Fast-mode Unit Min Typ Max Min Typ Max 【I 2C BUS format】 SCL clock frequency fSCL 0 - 100 0 - 400 kHz LOW period of the SCL clock tLOW 4.7 - - 1.3 - - μs HIGH period of the SCL clock tHIGH 4.0 - - 0.6 - - μs Hold time (repeated) START condition After this period, the first clock is generated tHD;STA 4.0 - - 0.6 - - μs Set-up time for a repeated START condition tSU;STA 4.7 - - 0.6 - - μs Data hold time tHD;DAT 0 - 3.45 0 - 0.9 μs Data set-up time tSU;DAT 250 - - 100 - - ns Set-up time for STOP condition tSU;STO 4.0 - - 0.6 - - μs Bus free time between a STOP and START condition tBUF 4.7 - - 1.3 - - μs |
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