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74LVC00AD Scheda tecnica(PDF) 5 Page - NXP Semiconductors |
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74LVC00AD Scheda tecnica(HTML) 5 Page - NXP Semiconductors |
5 / 14 page 74LVC00A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 — 25 April 2012 5 of 14 NXP Semiconductors 74LVC00A Quad 2-input NAND gate 10. Dynamic characteristics [1] Typical values are measured at Tamb =25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs 11. Waveforms Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max tpd propagation delay nA, nB to nY; see Figure 6 [2] VCC =1.2 V - 12 - - - ns VCC = 1.65 V to 1.95 V 0.3 3.8 8.4 0.3 9.7 ns VCC = 2.3 V to 2.7 V 1.0 2.2 4.8 1.0 5.7 ns VCC = 2.7 V 1.0 2.3 5.1 1.0 5.9 ns VCC = 3.0 V to 3.6 V 0.5 2.0 4.3 0.5 5.1 ns tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns CPD power dissipation capacitance per gate; VI =GND to VCC [4] VCC = 1.65 V to 1.95 V - 5.6 - - - pF VCC = 2.3 V to 2.7 V - 8.9 - - - pF VCC = 3.0 V to 3.6 V - 11.8 - - - pF VM = 1.5 V at VCC ≥ 2.7 V. VM =0.5 × VCC at VCC <2.7 V. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The input (nA, nB) to output (nY) propagation delays mna213 nA, nB input nY output tPHL tPLH VM VM VOL VOH GND VI |
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