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74ALVCH16901DGGRE4 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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74ALVCH16901DGGRE4 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 14 page SN74ALVCH16901 18BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010F − JULY 1995 − REVISED SEPTEMBER 2004 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VM VM VM VM VM VM VM VM VOH VOL th tsu From Output Under Test CL (see Note A) LOAD CIRCUIT S1 Open GND RL RL Output Control (low-level enabling) Output Waveform 1 S1 at VLOAD (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + V∆ VOH − V∆ 0 V VI 0 V 0 V tw VI VI VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. 0 V VI VM tPHL VM VM VI 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VM VM tPLH VLOAD VLOAD/2 1.8 V 2.5 V ± 0.2 V 2.7 V 3 V ± 0.3 V 1 k Ω 500 Ω 500 Ω 500 Ω VCC RL 2 × VCC 2 × VCC 6 V 6 V VLOAD CL 30 pF 30 pF 50 pF 50 pF 0.15 V 0.15 V 0.3 V 0.3 V V∆ VCC VCC 2.7 V 2.7 V VI VCC/2 VCC/2 1.5 V 1.5 V VM tr/tf ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns INPUT Figure 1. Load Circuit and Voltage Waveforms |
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