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ST16C654IJ68 Scheda tecnica(PDF) 6 Page - Exar Corporation |
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ST16C654IJ68 Scheda tecnica(HTML) 6 Page - Exar Corporation |
6 / 51 page ST16C654/654D xr 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2 6 FSRS# - - 76 I FIFO Status Register Select (active low input with internal pull-up). The content of the FSTAT register is placed on the data bus when this pin becomes active. However it should be noted, D0-D3 contain the inverted logic states of TXRDY# A-D pins, and D4-D7 the logic states (un-inverted) of RXRDY# A-D pins. A valid address is not required when reading this status register. MODEM OR SERIAL I/O INTERFACE TXA TXB TXC TXD 8 10 39 41 17 19 51 53 14 16 65 67 O UART channels A-D Transmit Data and infrared transmit data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during reset, or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is a logic 0. IRTXA IRTXB IRTXC IRTXD - - - - - - - - 6 24 57 75 O UART channel A-D Infrared Transmit Data. The inactive state (no data) for the Infrared encoder/decoder interface is a logic 0. Regardless of the logic state of MCR bit-6, this pin will be operating in the Infrared mode. RXA RXB RXC RXD 62 20 29 51 7 29 41 63 97 34 47 85 I UART channel A-D Receive Data or infrared receive data. Normal receive data input must idle at logic 1 condition. RTSA# RTSB# RTSC# RTSD# 5 13 36 44 14 22 48 56 11 19 62 70 O UART channels A-D Request-to-Send (active low) or general pur- pose output. This output must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], and IER[6]. Also see Figure 11. If these outputs are not used, leave them unconnected. CTSA# CTSB# CTSC# CTSD# 2 16 33 47 11 25 45 59 8 22 59 73 I UART channels A-D Clear-to-Send (active low) or general purpose input. It can be used for auto CTS flow control, see EFR[7], and IER[7]. Also see Figure 11. These inputs should be connected to VCC when not used. DTRA# DTRB# DTRC# DTRD# 3 15 34 46 12 24 46 58 9 21 60 72 O UART channels A-D Data-Terminal-Ready (active low) or general purpose output. If these outputs are not used, leave them uncon- nected. DSRA# DSRB# DSRC# DSRD# 1 17 32 48 10 26 44 60 7 23 58 74 I UART channels A-D Data-Set-Ready (active low) or general pur- pose input. This input should be connected to VCC when not used. This input has no effect on the UART. CDA# CDB# CDC# CDD# 64 18 31 49 9 27 43 61 99 32 49 83 I UART channels A-D Carrier-Detect (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. Pin Description NAME 64-LQFP PIN # 68-PLCC PIN# 100-QFP PIN # TYPE DESCRIPTION |
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