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74HCT7046A Scheda tecnica(PDF) 11 Page - NXP Semiconductors |
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74HCT7046A Scheda tecnica(HTML) 11 Page - NXP Semiconductors |
11 / 38 page December 1990 11 Philips Semiconductors Product specification Phase-locked-loop with lock detector 74HC/HCT7046A Phase comparator section Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) VI OTHER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. VIH DC coupled HIGH level input voltage SIGIN, COMPIN 1.5 3.15 4.2 1.2 2.4 3.2 1.5 3.15 4.2 1.5 3.15 4.2 V 2.0 4.5 6.0 VIL DC coupled LOW level input voltage SIGIN, COMPIN 0.8 2.1 2.8 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V 2.0 4.5 6.0 VOH HIGH level output voltage LD, PCnOUT 1.9 4.4 5.9 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 V 2.0 4.5 6.0 VIH or VIL −IO =20 µA −IO =20 µA −IO =20 µA VOH HIGH level output voltage LD, PCnOUT 3.98 5.48 4.32 5.81 3.84 5.34 3.7 5.2 V 4.5 6.0 VIH or VIL −I O = 4.0 mA −IO = 5.2 mA VOL LOW level output voltage LD, PCnOUT 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 2.0 4.5 6.0 VIH or VIL IO =20 µA IO =20 µA IO =20 µA VOL LOW level output voltage LD, PCnOUT 0.15 0.16 0.26 0.26 0.33 0.33 0.4 0.4 V 4.5 6.0 VIH or VIL IO = 4.0 mA IO = 5.2 mA ±II input leakage current SIGIN, COMPIN 3.0 7.0 18.0 30.0 4.0 9.0 23.0 38.0 5.0 11.0 27.0 45.0 µA 2.0 3.0 4.5 6.0 VCC or GND ±IOZ 3-state OFF-state current PC2OUT 0.5 5.0 10.0 µA 6.0 VIH or VIL VO =VCC or GND RI input resistance SIGIN, COMPIN 800 250 150 k Ω 3.0 4.5 6.0 VI at self-bias operating point; ∆VI = 0.5 V; see Figs 10, 11 and 12 |
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