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SN74ACT72231L20RJ Scheda tecnica(PDF) 10 Page - Texas Instruments |
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SN74ACT72231L20RJ Scheda tecnica(HTML) 10 Page - Texas Instruments |
10 / 21 page SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L 512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9 SYNCHRONOUS FIRST IN, FIRST OUT MEMORIES SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 REN1, REN2 OE WCLK tsk1 (see Note A) WEN2 (if applicable) WEN1 EF tpd(OE-Q) Q0 − Q8 W0 (1st valid write) W1 W2 W3 D0 − D8 tsu(D) tsu(EN) RCLK tpd(R-EF) W0 W1 ta ta ten Low NOTE A: tsk1 is the minimum time between a rising WCLK edge and a subsequent rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tsk1, then EF may not change state until the next RCLK edge. Figure 5. First-Data-Word-Latency Timing |
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