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FDD86113LZ Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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FDD86113LZ Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page ©2011 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDD86113LZ Rev. C1 Electrical Characteristics T J = 25 °C unless otherwise noted Off Characteristics On Characteristics Dynamic Characteristics Switching Characteristics Drain-Source Diode Characteristics Symbol Parameter Test Conditions Min Typ Max Units BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 V ΔBV DSS ΔT J Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C 72 mV/°C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±10 μA VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA1 1.5 3 V ΔV GS(th) ΔT J Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C -5 mV/°C rDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 4.2 A 87 104 m Ω VGS = 4.5 V, ID = 3.4 A 116 156 VGS = 10 V, ID = 4.2 A,TJ = 125 °C 142 170 gFS Forward Transconductance VDS = 5 V, ID = 4.2 A 9 S Ciss Input Capacitance VDS = 50 V, VGS = 0 V, f = 1MHz 213 285 pF Coss Output Capacitance 55 75 pF Crss Reverse Transfer Capacitance 2.4 5 pF Rg Gate Resistance 1.4 Ω td(on) Turn-On Delay Time VDD = 50 V, ID = 4.2 A, VGS = 10 V, RGEN = 6 Ω 3.6 10 ns tr Rise Time 1.3 10 ns td(off) Turn-Off Delay Time 9.7 20 ns tf Fall Time 1.6 10 ns Qg(TOT) Total Gate Charge VGS = 0 V to 10 V VDD = 50 V, ID = 4.2 A 3.7 6 nC Qg(TOT) Total Gate Charge VGS = 0 V to 4.5 V 1.9 3 Qgs Gate to Source Charge 0.6 nC Qgd Gate to Drain “Miller” Charge 0.7 nC VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 4.2 A (Note 2) 0.88 1.3 V VGS = 0 V, IS = 1.7 A (Note 2) 0.80 1.2 trr Reverse Recovery Time IF = 4.2 A, di/dt = 100 A/μs 31 49 ns Qrr Reverse Recovery Charge 20 33 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. Starting TJ = 25 °C, L = 1 mH, IAS = 5 A, VDD = 90 V, VGS = 10 V. 4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 40 °C/W when mounted on a 1 in2 pad of 2 oz copper a) 96 °C/W when mounted on a minimum pad of 2 oz copper b) |
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