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TS30022 Scheda tecnica(PDF) 8 Page - List of Unclassifed Manufacturers |
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TS30022 Scheda tecnica(HTML) 8 Page - List of Unclassifed Manufacturers |
8 / 19 page TRIUNE SYSTEMS PROPRIETARY & CONFIDENTIAL INFORMATION - 8 - TS30021/22/23 Version 1.5 Specifications subject to change WWW.TRIUNESYSTEMS.COM Copyright © 2013, Triune Systems, LLC The input to the FB pin is high impedance, and input current should be less than 100nA. As a result, good layout practices are required for the feedback resistors and feedback traces. When using the adjustable version, the feedback trace should be kept as short as possible and minimum width to reduce stray capacitance and to reduce the injection of noise. For the adjustable version, the ratio of VCC/Vout cannot exceed 16. Switching output, VSW This is the switching node of the regulator. It should be connected directly to the 1.5uH inductor with a wide, short trace and to one end of the Bootstrap capacitor. It is switching between VCC and PGND at the switching frequency. Ground, GND This ground is used for the majority of the device including the analog reference, control loop, and other circuits. Power Ground, PGND This is a separate ground connection used for the low side synchronous switch to isolate switching noise from the rest of the device. Enable, high-voltage, EN This is the input terminal to activate both the switching regulator and LDO. The input threshold is TTL/CMOS compatible. It also has an internal pull-up to ensure a stable state if the pin is disconnected. Option available for sequential power-up of switching regulator first, followed by activating the LDO after switching regulator voltage is above VOUT-UV threshold. PG Output, PG This is an open drain, active low output. The switched mode output voltage is monitored and the PG line will remain low until the output voltage reaches the VOUT-UV threshold. Once the internal comparator detects the output voltage is above the desired threshold, an internal delay timer is activated and the PG line is de-asserted to high once this delay timer expires. In the event the output voltage decreases below VOUT-UV, the PG line will be asserted low and remain low until the output rises above VOUT-UV and the delay timer times out. See Figure 2 for the circuit schematic for the PG signal. Options are available for PG only based on switcher output voltage, or the combination of both switcher and LDO outputs being higher than the VOUT-UV thresholds. Unregulated LDO input, VLDO This terminal is the unregulated input voltage source for regulation stage of the LDO. It is recommended that a 10uF bypass capacitor be placed close to the device for best performance. LDO Sense feedback, FBLDO This is the input terminal for the adjustable voltage feedback for the LDO. The following formula determines the output voltage. VOLDO = 0.8 (1 + RTOP/RBOT) The same guidelines as given for the switching regulator FB pin apply to the LDO FB pin as well. Regulated LDO Output, VOLDO This terminal is the output of the LDO and should be connected to a 1uF output capacitor. INTERNAL PROTECTION DETAILS SMPS Internal Current Limit The current through the high side FET is sensed on a cycle by cycle basis and if current limit is reached, it will abbreviate the cycle. In addition, the device senses the FB pin to identify hard short conditions and will direct the VSW output to skip 4 cycles if current limit occurs when FB is low. This allows current built up in the inductor during the minimum on time to decay sufficiently. Current limit is always active when the regulator is enabled. Soft start ensures current limit does not prevent regulator startup. |
Codice articolo simile - TS30022 |
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Descrizione simile - TS30022 |
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