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LMZ31506 Scheda tecnica(PDF) 5 Page - Texas Instruments |
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LMZ31506 Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 30 page PWRGD VIN PVIN PGND PH VOUT RT/CLK AGND VADJ INH/UVLO STSEL SS/TR VSENSE+ LMZ31506 PWRGD Logic + + VREF Current Share Power Stage and Control Logic Thermal Shutdown Shutdown Logic OCP VIN UVLO OSC w/PLL Comp ISHARE LMZ31506 www.ti.com SNVS993 – JUNE 2013 ELECTRICAL CHARACTERISTICS (continued) Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 6 A, CIN1 = 2 x 22 µF ceramic, CIN2 = 68 µF poly-tantalum, COUT1 = 4 x 47 µF ceramic (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ceramic 44 (5) CIN External input capacitance µF Non-ceramic 68(5) Ceramic 47 (6) 200 1500 µF COUT External output capacitance Non-ceramic 220(6) 5000 Equivalent series resistance (ESR) 35 m Ω (5) A minimum of 100µF of polymer tantalum and/or ceramic external capacitance is required across the input (VIN and PVIN connected) for proper operation. Locate the capacitor close to the device. See Table 4 for more details. When operating with split VIN and PVIN rails, place 4.7µF of ceramic capacitance directly at the VIN pin. (6) The amount of required output capacitance varies depending on the output voltage (see Table 3 ). The amount of required capacitance must include at least 1x 47µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 3 and Table 4 more details. DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMZ31506 |
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