ADRF6620ACPZ-R7 datasheet(2/52 Pages) AD

Il numero della parte	ADRF6620ACPZ-R7

Spiegazioni elettronici	700 MHz to 2700 MHz Rx Mixer with Integrated IF DGA, Fractional-N PLL, and VCO

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Produttore elettronici	AD [Analog Devices]

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ADRF6620

Data Sheet

Rev. 0 | Page 2 of 52

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

RF Input to IF DGA Output System Specifications................. 3

Synthesizer/PLL Specifications................................................... 4

RF Input to Mixer Output Specifications.................................. 6

IF DGA Specifications ................................................................. 7

Digital Logic Specifications......................................................... 8

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

RF Input to DGA Output System Performance ..................... 11

Phase-Locked Loop (PLL)......................................................... 13

RF Input to Mixer Output Performance ................................. 17

IF DGA ........................................................................................ 20

Spurious Performance................................................................ 22

Theory of Operation ...................................................................... 24

RF Input Switches....................................................................... 24

Tunable Balun ............................................................................. 25

RF Digital Step Attenuator (DSA)............................................ 25

Active Mixer................................................................................ 25

Digitally Programmable Variable Gain Amplifier (DGA).... 25

LO Generation Block ................................................................. 26

Serial Port Interface (SPI) ......................................................... 27

Basic Connections...................................................................... 28

RF Input Balun Insertion Loss Optimization......................... 30

IP3 and Noise Figure Optimization......................................... 31

Interstage Filtering Requirements............................................ 35

IF DGA vs. Load......................................................................... 38

ADC Interfacing......................................................................... 39

Power Modes............................................................................... 40

Layout .......................................................................................... 40

Register Map ................................................................................... 41

Register Address Descriptions...................................................... 42

Register 0x00, Reset: 0x00000, Name: SOFT_RESET ........... 42

Register 0x01, Reset: 0x8B7F, Name: Enables ........................ 42

Register 0x02, Reset: 0x0058, Name: INT_DIV..................... 43

Register 0x03, Reset: 0x0250, Name: FRAC_DIV ................. 43

Register 0x04, Reset: 0x0600, Name: MOD_DIV.................. 43

Register 0x20, Reset: 0x0C26, Name: CP_CTL...................... 44

Register 0x21, Reset: 0x0003, Name: PFD_CTL.................... 45

Register 0x22, Reset: 0x000A, Name: FLO_CTL ................... 46

Register 0x23, Reset: 0x0000, Name: DGA_CTL................... 47

Register 0x30, Reset: 0x00000, Name: BALUN_CTL............ 48

Register 0x31, Reset: 0x08EF, Name: MIXER_CTL .............. 48

Register 0x40, Reset: 0x0010, Name: PFD_CTL2.................. 49

Register 0x42, Reset: 0x000E, Name: DITH_CTL1............... 50

Register 0x43, Reset: 0x0001, Name: DITH_CTL2 ............... 50

Outline Dimensions....................................................................... 51

Ordering Guide .......................................................................... 51

REVISION HISTORY

7/13—Revision 0: Initial Version

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