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ADM1275-1ARQZ Scheda tecnica(PDF) 7 Page - Analog Devices |
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ADM1275-1ARQZ Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 48 page Data Sheet ADM1275 Rev. D | Page 7 of 48 SERIAL BUS TIMING CHARACTERISTICS tR = (VIL(MAX) – 0.15) to (VIH3V3 + 0.15) and tF = 0.9VDD to (VIL(MAX) – 0.15); where VIH3V3 = 2.1 V and VDD = 3.3 V. Table 2. Parameter Description Min Typ Max Unit Test Conditions/Comments fSCLK Clock frequency 400 kHz tBUF Bus free time 1.3 µs Following the stop condition of a read transaction 4.7 µs Following the stop condition of a write transaction tHD;STA Start hold time 0.6 µs tSU;STA Start setup time 0.6 µs tSU;STO Stop setup time 0.6 µs tHD;DAT SDA hold time 300 900 ns tSU;DAT SDA setup time 100 ns tLOW SCL low time 1.3 µs tHIGH SCL high time 0.6 µs tR SCL, SDA rise time 20 300 ns tF SCL, SDA fall time 20 300 ns Timing Diagram tLOW tBUF tHD;DAT tSU;DAT tSU;STA tHD;STA tHIGH tR tF tSU;STO P S S P VIH VIL VIH VIL SCL SDA Figure 2. Serial Bus Timing Diagram |
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