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AD2S83IPZ Scheda tecnica(PDF) 2 Page - Analog Devices |
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AD2S83IPZ Scheda tecnica(HTML) 2 Page - Analog Devices |
2 / 19 page AD2S83–SPECIFICATIONS Parameter Conditions Min Typ Max Unit SIGNAL INPUTS (SIN, COS) Frequency 1 0 20,000 Hz Voltage Level 1.8 2.0 2.2 V rms Input Bias Current 60 150 nA Input Impedance 1.0 M Ω REFERENCE INPUT (REF) Frequency 0 20,000 Hz Voltage Level 1.0 8.0 V pk Input Bias Current 60 150 nA Input Impedance 1.0 M Ω PERFORMANCE Repeatability 1 LSB Allowable Phase Shift (Signals to Reference) –10 +10 Degree Max Tracking Rate 10 Bits 1040 rps 12 Bits 260 rps 14 Bits 65 rps 16 Bits 16.25 rps Bandwidth User Selectable ACCURACY Angular Accuracy A, I 8 +1 LSB arc min Monotonicity Guaranteed Monotonic Missing Codes (16-Bit Resolution) A, I 4 Codes VELOCITY SIGNAL LINEARITY 2, 3, 4 AD2S83AP 0 kHz–500 kHz –40 °C to +85°C ±0.15 0.25 % FSR 0.5 MHz–1 MHz –40 °C to +85°C ±0.25 1.0 % FSR AD2S83IP 0 kHz–500 kHz –40 °C to +85°C ±0.25 0.5 % FSR 0.5 MHz–1 MHz –40 °C to +85°C ±0.25 1.0 % FSR Reversion Error AD2S83AP –40 °C to +85°C ±0.5 1.0 % O/P AD2S83IP –40 °C to +85°C ±1.0 1.5 % O/P DC Zero Offset 5 ±3mV Gain Scaling Accuracy ±1.5 3 % FSR Output Voltage 1 mA Load ±8V Dynamic Ripple Mean Value 1.0 % rms O/P INPUT/OUTPUT PROTECTION Analog Inputs Overvoltage Protection ±8V Analog Outputs Short Circuit O/P Protection ±5.6 ±8 ±10.4 mA DIGITAL POSITION Resolution 10, 12, 14, and 16 Bits Output Format Bidirectional Natural Binary Load 3 LSTTL INHIBIT6 Sense Logic LO to INHIBIT Time to Stable Data 240 390 490 ns ENABLE6 Logic LO Enables Position Output Logic HI Outputs in High ENABLE6/Disable Time Impedance State 35 110 ns BYTE SELECT 6 Sense Logic HI MS Byte DB1–DB8 Logic LO LS Byte DB1–DB8 Time to Data Available 60 140 ns SHORT CYCLE INPUTS Internally Pulled High via 100 k Ω to +V S SC1 SC2 0 0 10-Bit Resolution 0 1 12-Bit Resolution 1 0 14-Bit Resolution 1 1 16-Bit Resolution ( VS = 12 V dc 5%; VL = 5 V dc 10%; TA = –40 C to +85 C) –2– REV. E |
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