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AD9887APCB Scheda tecnica(PDF) 1 Page - Analog Devices |
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AD9887APCB Scheda tecnica(HTML) 1 Page - Analog Devices |
1 / 52 page Dual Interface for Flat Panel Display AD9887A Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved. FEATURES Analog interface 170 MSPS maximum conversion rate Programmable analog bandwidth 0.5 V to 1.0 V analog input range 500 ps p-p PLL clock jitter at 170 MSPS 3.3 V power supply Full sync processing Midscale clamping 4:2:2 output format mode Digital interface DVI 1.0-compatible interface 170 MHz operation (2 pixels/clock mode) High skew tolerance of 1 full input clock Sync detect for hot plugging Supports high bandwidth digital content protection APPLICATIONS RGB graphics processing LCD monitors and projectors Plasma display panels Scan converters Microdisplays Digital TVs GENERAL DESCRIPTION The AD9887A offers an analog interface receiver and a digital visual interface (DVI) receiver integrated on a single chip, supports high bandwidth digital content protection (HDCP), and is software and pin-to-pin compatible with the AD9887. Analog Interface The complete 8-bit, 170 MSPS, monolithic analog interface is optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 330 MHz support resolutions of up to 1600 × 1200 (UXGA) at 60 Hz. The interface includes a 170 MHz triple ADC with internal 1.25 V reference; a phase- locked loop (PLL); and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and Hsync. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V. The analog interface also offers full sync processing for composite sync and sync-on-green (SOG) appli- cations. The AD9887A on-chip PLL generates a pixel clock from Hsync with output frequencies ranging from 12 MHz to 170 MHz. PLL clock jitter is typically 500 ps p-p at 170 MSPS. FUNCTIONAL BLOCK DIAGRAM HSYNC COAST CLAMP CKINV CKEXT FILT VSYNC SERIAL REGISTER AND POWER MANAGEMENT SCL SDA A1 A0 DATACK HSOUT VSOUT SOGOUT Rx0+ Rx0– Rx1+ Rx1– Rx2+ Rx2– RxC+ RxC– DVI RECEIVER AD9887A DIGITAL INTERFACE SYNC PROCESSING AND CLOCK GENERATION ANALOG INTERFACE SCDT REFIN DDCSCL DDCSDA MCL MDA HDCP SOGIN RED A RED B GREEN A GREEN B BLUE A BLUE B HSOUT VSOUT SOGOUT DE DATACK REFOUT RAIN CLAMP 8 8 8 GAIN CLAMP 8 8 8 BAIN CLAMP 8 8 8 2 DATACK 2 REF ROUTA ROUTB GOUTA GOUTB BOUTA 8 8 8 8 8 8 2 8 8 8 8 8 8 8 8 8 ROUTA ROUTB GOUTA GOUTB BOUTA BOUTB RTERM DE HSOUT VSOUT A/D A/D A/D Figure 1. Digital Interface The AD9887A contains a DVI 1.0-compatible receiver and supports resolutions up to 1600 × 1200 (UXGA) at 60 Hz. The receiver operates with true color (24-bit) panels in one or two pixel(s) per clock mode and features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can receive encrypted video content. The AD9887A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of authentication during transmission, as specified by the HDCP v1.0 protocol. Fabricated in an advanced CMOS process, the AD9887A is provided in a 160-lead, surface-mount, plastic MQFP and is specified over the 0°C to 70°C temperature range. The AD9887A is also available in an RoHS compliant package. |
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