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74LVC125APW Scheda tecnica(PDF) 7 Page - NXP Semiconductors |
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74LVC125APW Scheda tecnica(HTML) 7 Page - NXP Semiconductors |
7 / 16 page 74LVC125A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7 — 11 April 2013 7 of 16 NXP Semiconductors 74LVC125A Quad buffer/line driver with 5 V tolerant input/outputs; 3-state 11. AC waveforms Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The input nA to output nY propagation delays mna230 tPHL tPLH VM VM nA input nY output GND VI VOH VOL Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. 3-state enable and disable times mna362 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nOE input VI VOL VOH VCC VM GND GND tPZL tPZH VM VM Table 8. Measurement points Supply voltage Input Output VCC VI VM VM 1.2 V VCC 0.5 V CC 0.5 V CC 1.65 V to 1.95 V VCC 0.5 V CC 0.5 V CC 2.3 V to 2.7 V VCC 0.5 V CC 0.5 V CC 2.7 V 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V |
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