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74LVC125APW Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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74LVC125APW Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 74LVC125A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7 — 11 April 2013 3 of 16 NXP Semiconductors 74LVC125A Quad buffer/line driver with 5 V tolerant input/outputs; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO14 and (T)SSOP14 Fig 5. Pin configuration for DHVQFN14 125 1OE VCC 1A 4OE 1Y 4A 2OE 4Y 2A 3OE 2Y 3A GND 3Y 001aad045 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aad046 125 GND(1) Transparent top view 2Y 3A 2A 3OE 2OE 4Y 1Y 4A 1A 4OE 6 9 5 10 4 11 3 12 2 13 terminal 1 index area Table 2. Pin description Symbol Pin Description 1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 data enable input (active LOW) 1A, 2A, 3A, 4A 2, 5, 9, 12 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage Table 3. Function selection[1] Inputs Output nOE nA nY LLL LH H HX Z |
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