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ST33G1M2 Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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ST33G1M2 Scheda tecnica(HTML) 1 Page - STMicroelectronics |
1 / 4 page October 2013 DocID025293 Rev 1 1/4 ST33G1M2 Secure MCU with 32-bit ARM® SecurCore® SC300™ CPU and high-density Flash memory Data brief Features Hardware features ARM® SecurCore® SC300™ 32-bit RISC core cadenced at 25 MHz 30 Kbytes of User RAM Up to 1280 Kbytes of User Flash memory with OTP area Asynchronous receiver transmitter supporting ISO/IEC 7816-3 T=0 and T=1 protocols (Slave mode supported) Single Wire Protocol (SWP) Interface for communications with NFC router (ETSI 102-613 compliant) Serial peripheral interface (SPI) master/slave interface Three 16-bit timers with interrupt capability Seven general purpose I/Os enabling proprietary protocol implementation 1.8 V, 3 V and 5 V supply voltage ranges External clock frequency from 1 up to 10 MHz Current consumption compatible with GSM and ETSI specifications Power-saving standby state Contact assignment compatible with ISO/IEC 7816-2 ESD protection greater than 4 kV (HBM) Software features Secure Flash Loader Flash drivers MIFARE™ libraries: Classic, DESFire EV1, and Plus Security features Active shield Memory protection unit (MPU) Monitoring of environmental parameters Protection against faults 16- and 32-bit CRC calculation block (ISO 13239, IEEE 802.3, etc.) True random number generator Unique serial number on each die Hardware security-enhanced DES accelerator Hardware security-enhanced AES accelerator MIFARE Classic™ cryptography hardware accelerator NESCRYPT coprocessor for public key cryptography algorithm Applications ST33G1M2 major applications include: Mobile communications (GSM, 3G and CDMA) Java Card applications Multimedia www.st.com |
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