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AD5323BRU-REEL Scheda tecnica(PDF) 6 Page - Analog Devices

Il numero della parte AD5323BRU-REEL
Spiegazioni elettronici  2.5 V to 5.5 V, 230 關A, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5323BRU-REEL Scheda tecnica(HTML) 6 Page - Analog Devices

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AD5303/AD5313/AD5323
Rev. B | Page 6 of 28
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A, B Version3
Parameter2
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
VREF = VDD = 5 V
AD5303
6
8
μs
¼ scale to ¾ scale change (0x40 to 0xc0)
AD5313
7
9
μs
¼ scale to ¾ scale change (0x100 to 0x300)
AD5323
8
10
μs
¼ scale to ¾ scale change (0x400 to 0xc00)
Slew Rate
0.7
V/μs
Major-Code Transition Glitch Energy
12
nV-s
1 LSB change around major carry
(011 . . . 11 to 100 . . . 00)
Digital Feedthrough
0.10
nV-s
Analog Crosstalk
0.01
nV-s
DAC-to-DAC Crosstalk
0.01
nV-s
Multiplying Bandwidth
200
kHz
VREF = 2 V ± 0.1 V p-p, unbuffered mode
Total Harmonic Distortion
−70
dB
VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range for Version A and Version B: −40°C to +105°C.
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
Parameter1, 2, 3
(A, B Version)
Unit
Conditions/Comments
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
13
ns min
SCLK low time
t4
0
ns min
SYNC to SCLK rising edge setup time
t5
5
ns min
Data setup time
t6
4.5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
100
ns min
Minimum SYNC high time
t9
20
ns min
LDAC pulse width
t10
20
ns min
SCLK falling edge to LDAC rising edge
t11
20
ns min
CLR pulse width
t124, 5
5
ns min
SCLK falling edge to SDO invalid
t134, 5
20
ns max
SCLK falling edge to SDO valid
t145
0
ns min
SCLK falling edge to SYNC rising edge
t155
10
ns min
SYNC rising edge to SCLK rising edge
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 4 and Figure 5.
4 These are measured with the load circuit of Figure 4.
5 Daisy-chain mode only (see Figure 47).


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