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ADRF6850BCPZ Scheda tecnica(PDF) 1 Page - Analog Devices |
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ADRF6850BCPZ Scheda tecnica(HTML) 1 Page - Analog Devices |
1 / 36 page 100 MHz to 1000 MHz Integrated Broadband Receiver ADRF6850 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. FEATURES IQ quadrature demodulator Integrated fractional-N PLL and VCO Gain control range: 60 dB Input frequency range: 100 MHz to 1000 MHz Input P1dB: +12 dBm at 0 dB gain Input IP3: +22.5 dBm at 0 dB gain Noise figure: 11 dB at >39 dB gain, 49 dB at 0 dB gain Baseband 1 dB bandwidth: 250 MHz in wideband mode, 50 MHz in narrow-band mode SPI/I2C serial interface Power supply: +3.3 V/350 mA APPLICATIONS Broadband communications Cellular communications Satellite communications GENERAL DESCRIPTION The ADRF6850 is a highly integrated broadband quadrature demodulator, frequency synthesizer, and variable gain amplifier (VGA). The device covers an operating frequency range from 100 MHz to 1000 MHz for use in both narrow-band and wideband communications applications, performing quadrature demodu- lation from IF directly to baseband frequencies. The ADRF6850 demodulator includes a high modulus fractional-N frequency synthesizer with integrated VCO, providing better than 1 Hz frequency resolution, and a 60 dB gain control range provided by a front-end VGA. Control of all the on-chip registers is through a user-selected SPI interface or I2C interface. The device operates from a single power supply ranging from 3.15 V to 3.45 V. FUNCTIONAL BLOCK DIAGRAM QBB QBB RSET SDI/SDA CLK/SCL SDO CS GND MUXOUT ×2 DOUBLER 5-BIT DIVIDER REFERENCE CHARGE PUMP CURRENT SETTING REFIN ÷2 PHASE FREQUENCY DETECTOR SEQUENCED GAIN INTERFACE + – DRIVER VCO CORE 0°/90° VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 LOMON LOMON ADRF6850 RFI RFI RFCM VGAIN 60dB GAIN CONTROL RANGE N-COUNTER INTEGER REGISTER FRACTIONAL REGISTER MODULUS 225 THIRD-ORDER FRACTIONAL INTERPOLATOR RFCP4 RFCP3 RFCP2 RFCP1 CP LF3 LF2 LDET TESTLO TESTLO IBB IBB CCOMP1 CCOMP2 CCOMP3 VTUNE VOCM SPI/ I2C INTERFACE RFDIV Figure 1. |
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