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ML4823CS Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor

Il numero della parte ML4823CS
Spiegazioni elettronici  High Frequency Power Supply Controller
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

ML4823CS Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor

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May 1997
ML4823
High Frequency Power Supply Controller
FEATURES
s
Practical operation at switching frequencies to 1.0MHz
s
High current (2A peak) totem pole output
s
Wide bandwidth error amplifier
s
Fully latched logic with double pulse suppression
s
Pulse-by-pulse current limiting
s
Soft start and max. duty cycle control
s
Under voltage lockout with hysteresis
s
5.1V trimmed bandgap reference
s
Low start-up current (1.1mA)
s
Pin compatible improved replacement for UC3823
s
Fast shut down path from current limit to output
s
Soft start latch ensures full soft start cycle
s
Outputs pull low for undervoltage lockout
GENERAL DESCRIPTION
The ML4823 High Frequency PWM Controller is an IC
controller optimized for use in Switch Mode Power
Supply designs running at frequencies to 1MHz.
Propagation delays are minimal through the comparators
and logic for reliable high frequency operation while slew
rate and bandwidth are maximized on the error amplifier.
This controller is designed for single-ended applications
using voltage or current mode and provides for input
voltage feed forward.
A 1V threshold current limit comparator provides cycle-
by-cycle current limit and exceeding a 1.4V threshold
initiates a soft-start cycle. The soft start pin doubles as a
maximum duty cycle clamp. All logic is fully latched to
provide jitter-free operation and prevent multiple pulsing.
An under-voltage lockout circuit with 800mV of hysteresis
assures low startup current and drives the outputs low
during fault conditions.
This controller is an improved second source for the
UC3823 controller; however, the ML4823 includes
features not found on the 3823. These features are set in
italics.
BLOCK DIAGRAM (Pin Configuration Shown for 16-Pin Version)
5
6
OSC
RT
CT
4
7
3
RAMP
E/A OUT
COMP
+
+
1.25V
S
R
Q
13
14
12
ERROR
AMP
+
2
1
NI
INV
POWER VC
OUTPUT
POWER GND
CLOCK OUT
8
SOFT START
V+
+
1V
11
9
ILIM REF
ILIM/S.D.
+
1.4V
+
S
R
Q
4V
5.1V
+
16
5.1V VREF
+
ENABLE
VREF
15
VCC
UNDER
VOLTAGE
LOCKOUT
9V
VREF GEN
10
SIGNAL GND
INTERNAL
BIAS
REV. 1.0 10/12/2000


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