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ML4800 Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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ML4800 Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 14 page ML4800 2 REV. 1.0.2 3/7/2001 PIN CONFIGURATION PIN DESCRIPTION PIN NAME FUNCTION 9 DC ILIMIT PWM cycle-by-cycle current limit comparator input 10 GND Ground 11 PWM OUT PWM driver output 12 PFC OUT PFC driver output 13 VCC Positive supply 14 VREF Buffered output for the internal 7.5V reference 15 VFB PFC transconductance voltage error amplifier input 16 VEAO PFC transconductance voltage error amplifier output PIN NAME FUNCTION 1 IEAO Slew rate enhanced PFC transconductance error amplifier output 2IAC PFC AC line reference input to Gain Modulator 3ISENSE Current sense input to the PFC Gain Modulator 4VRMS PFC Gain Modulator RMS line voltage compensation input 5 SS Connection point for the PWM soft start capacitor 6VDC PWM voltage feedback input 7 RAMP 1 Oscillator timing node; timing set by RTCT 8 RAMP 2 When in current mode, this pin functions as the current sense input; when in voltage mode, it is the PWM modulation ramp input. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IEAO IAC ISENSE VRMS SS VDC RAMP 1 RAMP 2 VEAO VFB VREF VCC PFC OUT PWM OUT GND DC ILIMIT TOP VIEW ML4800 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) |
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