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ML2003CP Scheda tecnica(PDF) 7 Page - Fairchild Semiconductor |
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ML2003CP Scheda tecnica(HTML) 7 Page - Fairchild Semiconductor |
7 / 11 page PRODUCT SPECIFICATION ML2003, ML2004 REV. 1.1.1 3/19/01 7 Functional Description The ML2003 consists of a coarse gain stage, a fine gain stage, an output buffer, and a serial/parallel digital interface. Gain Stages The analog input, VIN, goes directly into the op amp input in the coarse gain stage. The coarse gain stage has a gain range of 0 to 22.5dB in 1.5dB steps. The fine gain stage is cascaded onto the coarse section. The fine gain stage has a gain range of 0 to 1.5dB in 0.1dB steps. In addition, both sections can be programmed for either gain or attenuation, thus doubling the effective gain range. The logarithmic steps in each gain stage are generated by placing the input signal across a resistor string of 16 series resistors. Analog switches allow the voltage to be tapped from the resistor string at 16 points. The resistors are sized such that each output voltage is at the proper logarithimic ratio relative to the input signal at the top of the string. Atten- uation is implemented by using the resistor string as a simple voltage divider, and gain is implemented by using the resis- tor string as a feedback resistor around an internal op amp. Gain Settings Since the coarse and fine gain stages are cascaded, their gains can be summed logarithmically. Thus, any gain from –24dB to +24dB in 0.1dB steps can be obtained by combining the coarse and fine gain settings to yield the desired gain setting. The relationship between the digital select bits and the corre- sponding analog gain values is shown in Tables 1 and 2. Note that C3-C0 selects the coarse gain, F3-F0 selects the fine gain, and ATTEN/GAIN selects either attenuation or gain. Output Buffer The final analog stage is the output buffer. This amplifier has internal gain of 1 and is designed to drive 600 ohms and 100pF loads. Thus, it is suitable for driving a telephone hybrid circuit directly without any external amplifier. Power Supplies The digital section is powered between VCC and GND, or 5 volts. The analog section is powered between VCC and VSS and uses AGND as the reference point, or ±5 volts. GND and AGND are totally isolated inside the device to minimize coupling from the digital section into the analog section. However, AGND and GND should be tied together physically near the device and ideally close to the common power supply ground connection. Typically, the power supply rejection of VCC and VSS to the analog output is greater than –60dB at 1 kHz. If decoupling of the power supplies is still necessary in a system, VCC and VSS should be decoupled with respect to AGND. Powerdown Mode A powerdown mode can be selected with pin PDN. When PDN = 1, the device is powered down. In this state, the power consumption is reduced by removing power from the analog section and forcing the analog output,VOUT, to a high impedance state. While the device is in powerdown mode, the digital section is still functional and the current data word remains stored in the latch when in serial mode. When PDN = 0, the device is in normal operation. Digital Section The ML2003 can be operated with a serial or parallel interface. The SER/PAR pin selects the desired interface. When SER/PAR = 1, the serial mode is selected. When SER/PAR = 0, the parallel mode is selected. The ML2004 digital interface is serial only. Serial Mode Serial mode is selected by setting SER/PAR pin high. The serial interface allows the gain settings to be set from a serial data word. The timing for the serial mode is shown in Figure 10. The serial input data, SID, is loaded into a shift register on rising edges of the shift clock, SCK. The data can be parallel loaded into a latch when the input latch signal, LATI, is high. The LATI pulse must occur when SCK is low. In this way, a new data word can be loaded into the shift register without disturbing the existing data word in the latch. The parallel outputs of the latch control the attenuation/gain setting. The order of the data word bits in the latch is shown in Figure 11. Note that bit 0 is the first bit of the data word clocked into the shift register. Tables 1 and 2 describe how the data word programs the gain. Table 1. Fine Gain Settings (C3-C0 = 0) F3 F2 F1 F0 Ideal Gain (dB) ATTEN/GAIN = 1 ATTEN/GAIN = 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -.1 -.2 -.3 -.4 -.5 -.6 -.7 -.8 -.9 -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0 1.1 1.2 1.3 1.4 1.5 |
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