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ST1CC40PUR Scheda tecnica(PDF) 10 Page - STMicroelectronics |
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ST1CC40PUR Scheda tecnica(HTML) 10 Page - STMicroelectronics |
10 / 37 page Functional description ST1CC40 10/37 DocID18279 Rev 5 5.1 Power supply and voltage reference The internal regulator circuit consists of a startup circuit, an internal voltage pre-regulator, the BandGap voltage reference and the bias block that provides current to all the blocks. The starter supplies the startup current to the entire device when the input voltage goes high and the device is enabled (INHIBIT pin connected to ground). The pre-regulator block supplies the bandgap cell with a pre-regulated voltage that has a very low supply voltage noise sensitivity. 5.2 Voltage monitor An internal block continuously senses the Vcc, Vref and Vbg. If the monitored voltages are good, the regulator begins operating. There is also a hysteresis on the VCC (UVLO). Figure 4. Internal circuit 5.3 Soft-start The startup phase is implemented ramping the reference of the embedded error amplifier in 1 msec typ. time. It minimizes the inrush current and decreases the stress of the power components at power-up. During normal operation a new soft-start cycle takes place in case of: Thermal shutdown event UVLO event. 5.4 Error amplifier The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non-inverting input is connected to the internal voltage reference (100 mV), while the inverting input (FB) is connected to the output current sensing resistor. The error amplifier is internally compensated to minimize the size of the final application. STARTER PREREGULATOR IC BIAS BANDGAP VREF VREG Vcc D00IN126 AM12803v1 |
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