PRODUCT SPECIFICATION

ML4800

REV. 1.0.5 9/25/01

11

is the desired start-up delay.

It is important that the time constant of the PWM soft-start

allow the PFC time to generate sufficient output power for

the PWM section. The PWM start-up delay should be at least

5ms.

Caution should be exercised when using this minimum soft

start capacitance value because premature charging of the SS

capacitor and activation of the PWM section can result if

line voltage and nominal PFC output voltage. Typically, a

out to reach their nominal values prior to activation of the

PWM section at line voltages between 90Vrms and

265Vrms.

The ML4800 is a voltage-fed part. It requires an external

15V, ±10% (or better) shunt voltage regulator, or some other

15V nominal. This allows low power dissipation while at the

same time delivering 13V nominal gate drive at the PWM

OUT and PFC OUT outputs. If using a Zener diode for this

function, it is important to limit the current through the

Zener to avoid overheating or destroying it. This can be

easily done with a single resistor in series with the Vcc pin,

returned to a bias supply of typically 18V to 20V. The

resistor’s value must be chosen to meet the operating current

requirement of the ML4800 itself (8.5mA, max.) plus the

current required by the two gate driver outputs.

EXAMPLE:

a total gate charge of 90nC at 100kHz (e.g., 1 IRF840

MOSFET and 2 IRF820 MOSFETs), the gate driver current

required is:

The ML4800 should be locally bypassed with a 1.0µF

ceramic capacitor. In most applications, an electrolytic

capacitor of between 47µF and 220µF is also required across

the part, both for filtering and as part of the start-up bootstrap

circuitry.

Css

5ms

25

µA

1.25V

---------------

×

100nF

==

(6a)

I

GATEDRIVE

100kHz

90nC

×

9mA

==

(7)

R

BIAS

V

BIAS

V

CC

–

I

CC

I

G

I

Z

++

---------------------------------

=

(8)

R

BIAS

20V

15V

–

6mA

9mA

5mA

++

--------------------------------------------------

250

Ω

==

Figure 4. Typical Trailing Edge Control Scheme

RAMP

VEAO

TIME

VSW1

TIME

REF

EA

–

+

–

+

OSC

DFF

R

D

Q

Q

CLK

U1

RAMP

CLK

U4

U3

C1

RL

I4

SW2

SW1

+

DC

I1

I2

I3

VIN

L1

U2