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74ALVCH16601DGVRG4 Scheda tecnica(PDF) 1 Page - Texas Instruments

Il numero della parte 74ALVCH16601DGVRG4
Spiegazioni elettronici  18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

74ALVCH16601DGVRG4 Scheda tecnica(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)
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OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
CLKENAB
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027F – JULY 1995 – REVISED OCTOBER 2004
Member of the Texas Instruments Widebus™
Family
UBT™ (Universal Bus Transceiver) Combines
D-Type Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, Clocked,
or Clock-Enabled Modes
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
This 18-bit universal bus transceiver is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH16601 combines D-type latches and
D-type flip-flops to allow data flow in transparent,
latched, and clocked modes.
Data
flow
in
each
direction
is
controlled
by
output-enable
(OEAB
and
OEBA),
latch-enable
(LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs.
The
clock
can
be
controlled
by
the
clock-enable (CLKENAB and CLKENBA) inputs. For
A-to-B
data
flow,
the
device
operates
in
the
transparent mode when LEAB is high. When LEAB is
low, the A data is latched if CLKAB is held at a high
or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of
CLKAB. Output enable OEAB is active low. When
OEAB is low, the outputs are active. When OEAB is
high, the outputs are in the high-impedance state.
<br/>
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16601 is characterized for operation from -40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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