Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

AD5443YRM-REEL Scheda tecnica(PDF) 7 Page - Analog Devices

Il numero della parte AD5443YRM-REEL
Spiegazioni elettronici  8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5443YRM-REEL Scheda tecnica(HTML) 7 Page - Analog Devices

Back Button AD5443YRM-REEL Datasheet HTML 3Page - Analog Devices AD5443YRM-REEL Datasheet HTML 4Page - Analog Devices AD5443YRM-REEL Datasheet HTML 5Page - Analog Devices AD5443YRM-REEL Datasheet HTML 6Page - Analog Devices AD5443YRM-REEL Datasheet HTML 7Page - Analog Devices AD5443YRM-REEL Datasheet HTML 8Page - Analog Devices AD5443YRM-REEL Datasheet HTML 9Page - Analog Devices AD5443YRM-REEL Datasheet HTML 10Page - Analog Devices AD5443YRM-REEL Datasheet HTML 11Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 24 page
background image
Data Sheet
AD5426/AD5432/AD5443
Rev. G | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUT1 1
IOUT2 2
GND
3
SCLK
4
SDIN
5
RFB
10
VREF
9
VDD
8
SDO
7
SYNC
6
AD5426/
AD5432/
AD5443
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
IOUT1
DAC Current Output.
2
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
GND
Digital Ground Pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into
the shift register on the rising edge of SCLK. The device can accommodate clock rates up to 50 MHz.
5
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to rising edge.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the mode, the serial
interface counts clocks, and data is latched to the shift register on the 16th active clock edge.
7
SDO
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active
clock edge. SDO operates with a VDD of 3.0 V to 5.5 V.
8
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
9
VREF
DAC Reference Voltage Input.
10
RFB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.


Codice articolo simile - AD5443YRM-REEL

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Analog Devices
AD5443YRM-REEL AD-AD5443YRM-REEL Datasheet
553Kb / 24P
   8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
REV. 0
AD5443YRM-REEL7 AD-AD5443YRM-REEL7 Datasheet
553Kb / 24P
   8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
REV. 0
More results

Descrizione simile - AD5443YRM-REEL

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Analog Devices
AD5432 AD-AD5432_15 Datasheet
987Kb / 25P
   8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
Rev. G
AD5443 AD-AD5443_15 Datasheet
987Kb / 25P
   8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
Rev. G
AD5426 AD-AD5426_15 Datasheet
987Kb / 25P
   8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
Rev. G
AD5426 AD-AD5426 Datasheet
553Kb / 24P
   8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
REV. 0
AD5452 AD-AD5452_15 Datasheet
725Kb / 28P
   8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface
Rev. G
AD5449YRUZ AD-AD5449YRUZ Datasheet
619Kb / 32P
   Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface
REV. C
AD5451 AD-AD5451_15 Datasheet
725Kb / 28P
   8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface
Rev. G
AD5453 AD-AD5453_15 Datasheet
725Kb / 28P
   8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface
Rev. G
AD5429 AD-AD5429_13 Datasheet
717Kb / 28P
   Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface
Rev. E
AD5453YRMZ AD-AD5453YRMZ Datasheet
725Kb / 28P
   8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface
Rev. G
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com