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ADF7023BCPZ Scheda tecnica(PDF) 5 Page - Analog Devices

Il numero della parte ADF7023BCPZ
Spiegazioni elettronici  High Performance, Low Power, ISM Band FSK/GFSK/OOK/MSK/GMSK Transceiver IC
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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ADF7023BCPZ Scheda tecnica(HTML) 5 Page - Analog Devices

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Data Sheet
ADF7023
Rev. C | Page 5 of 112
The communications processor provides support for generic
packet formats. The packet format is highly flexible and fully
programmable, thereby ensuring its compatibility with
proprietary packet profiles. In transmit mode, the commun-
ications processor can be configured to add preamble, sync
word, and CRC to the payload data stored in packet RAM. In
receive mode, the communications processor can detect and
interrupt the host processor on reception of preamble, sync
word, address, and CRC and store the received payload to
packet RAM. The ADF7023 uses an efficient interrupt system
comprising MAC level interrupts and PHY level interrupts that
can be individually set. The payload data plus the 16-bit CRC
can be encoded/decoded using Manchester or 8b/10b encoding.
Alternatively, data whitening and dewhitening can be applied.
The smart wake mode (SWM) allows the ADF7023 to wake up
autonomously from sleep using the internal wake-up timer
without intervention from the host processor. After wake-up,
the ADF7023 is controlled by the communications processor.
This functionality allows carrier sense, packet sniffing, and
packet reception while the host processor is in sleep, thereby
reducing overall system current consumption. The smart wake
mode can wake the host processor on an interrupt condition.
These interrupt conditions can be configured to include the
reception of valid preamble, sync word, CRC, or address match.
Wake-up from sleep mode can also be triggered by the host
processor. For systems requiring very accurate wake-up timing,
a 32 kHz oscillator can be used to drive the wake-up timer.
Alternatively, the internal RC oscillator can be used, which gives
lower current consumption in sleep.
The ADF7023 features an advanced encryption standard (AES)
engine with hardware acceleration that provides 128-bit block
encryption and decryption with key sizes of 128 bits, 192 bits,
and 256 bits. Both electronic code book (ECB) and Cipher
Block Chaining Mode 1 (CBC Mode 1) are supported. The AES
engine can be used to encrypt/decrypt packet data and can be
used as a standalone engine for encryption/decryption by the
host processor. The AES engine is enabled on the ADF7023 by
downloading the AES software module to program RAM. The
AES software module is available from Analog Devices, Inc.
An on-chip, 8-bit ADC provides readback of an external analog
input, the RSSI signal, or an integrated temperature sensor. An
integrated battery voltage monitor raises an interrupt flag to the
host processor whenever the battery voltage drops below a user-
defined threshold.


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