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TS555IPT Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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TS555IPT Scheda tecnica(HTML) 1 Page - STMicroelectronics |
1 / 20 page November 2008 Rev 2 1/20 20 TS555 Low power single CMOS timer Features ■ Very low power consumption: 110 µA typ at VCC = 5 V 90 µa typ at VCC = 3 V ■ High maximum astable frequency of 2.7 MHz ■ Pin-to-pin functionally-compatible with bipolar NE555 ■ Wide voltage range: +2 V to +16 V ■ Supply current spikes reduced during output transitions ■ High input impedance: 1012 Ω ■ Output compatible with TTL, CMOS and logic MOS Description The TS555 is a single CMOS timer with a very low consumption: (Icc(TYP) TS555 = 110 µA at VCC = +5 V versus Icc(TYP) NE555 = 3 mA), and high frequency: (ff(max.) TS555 = 2.7 MHz versus f(max) NE555 = 0.1 MHz). Timing remains accurate in both monostable and astable mode. The TS555 provides reduced supply current spikes during output transitions, which enable the use of lower decoupling capacitors compared to those required by bipolar NE555. With the high input impedance (1012 Ω), timing capacitors can also be minimized. N DIP8 (Plastic package) D SO8 (Plastic micropackage) P TSSOP8 (Thin shrink small outline package) 1 2 3 4 8 7 6 5 GND Trigger Output Reset CC Control Voltage V Discharge Threshold Pin connections (top view) www.st.com |
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