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FIN1108TMTD Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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FIN1108TMTD Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Pin Descriptions Function Table H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance Connection Diagram Functional Diagram Pin Name Description RIN1+, RIN2+, RIN3+, RIN4+, RIN5+, RIN6+, RIN7+, RIN8+ Non-inverting LVDS Input RIN1−, RIN2−, RIN3−, RIN4−, RIN5−, RIN6−, RIN7−, RIN8− Inverting LVDS Input DOUT1+, DOUT2+, DOUT3+, DOUT4+, DOUT5+, DOUT6+, DOUT7+, DOUT8+ Non-inverting Driver Output DOUT1−, DOUT2−, DOUT3−, DOUT4−, DOUT5−, DOUT6−, DOUT7−, DOUT8− Inverting Driver Output EN Driver Enable Pin for All Output EN12 Inverting Driver Enable Pin for DOUT1 and DOUT2 EN34 Inverting Driver Enable Pin for DOUT3 and DOUT4 EN56 Inverting Driver Enable Pin for DOUT5 and DOUT6 EN78 Inverting Driver Enable Pin for DOUT7 and DOUT8 VCC Power Supply GND Ground VBB Reference Voltage Output Inputs Outputs EN ENxx DIN+ DIN− DOUT+ DOUT− H L HL HL H L LH LH H L Fail Safe Case H L XH X X ZZ LX X X Z Z |
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