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AD5270BRMZ-50 Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD5270BRMZ-50 Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 24 page Data Sheet AD5270/AD5271 Rev. F | Page 7 of 24 INTERFACE TIMING SPECIFICATIONS VDD = 2.5 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. Parameter Limit1 Unit Test Conditions/Comments t12 20 ns min SCLK cycle time t2 10 ns min SCLK high time t3 10 ns min SCLK low time t4 15 ns min SYNC to SCLK falling edge setup time t5 5 ns min Data setup time t6 5 ns min Data hold time t7 1 ns min SCLK falling edge to SYNC rising edge t83, 4 500 ns min Minimum SYNC high time t9 15 ns min SYNC rising edge to next SCLK fall ignored t105 450 ns max SCLK rising edge to SDO valid tRDAC_R-PERF 2 μs max RDAC register write command execute time tRDAC_NORMAL 600 ns max RDAC register write command execute time tMEMORY_READ 6 μs max Memory readback execute time tMEMORY_PROGRAM 350 ms max Memory program time tRESET 0.6 ms max Reset 50-TP restore time tPOWER-UP6 2 ms max Power-on 50-TP restore time 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 50 MHz. 3 Refer to tRDAC_R-PER and tRDAC_NORMAL for RDAC register write operations. 4 Refer to t MEMORY_READ and tMEMORY_PROGRAM for memory commands operations. 5 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF. 6 Maximum time after VDD − VSS is equal to 2.5 V. Shift Register and Timing Diagrams DATA BITS DB9 (MSB) DB0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 CONTROL BITS C0 C1 C2 D9 D8 C3 0 0 Figure 2. Shift Register Content 0 0 C3 C2 D7 D6 D5 D2 D1 D0 SCLK SDO DIN SYNC t7 t9 t1 t2 t4 t3 t8 t5 t6 Figure 3. Write Timing Diagram (CPOL = 0, CPHA = 1) |
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