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AD5340BRUZ-REEL1 Scheda tecnica(PDF) 9 Page - Analog Devices

Il numero della parte AD5340BRUZ-REEL1
Spiegazioni elettronici  2.5 V to 5.5 V, 115 關A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5340BRUZ-REEL1 Scheda tecnica(HTML) 9 Page - Analog Devices

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AD5330/AD5331/AD5340/AD5341
Rev. A | Page 9 of 28
BUFFER
12-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
POWER-DOWN
LOGIC
CS
WR
CLR
LDAC
VREF
VDD
VOUT
PD
GND
AD5340
POWER-ON
RESET
RESET
12
11
9
8
4
14
5
13
7
DB10
DB9
DB0
..
15
24
1
DB11 2
BUF 3
GAIN 10
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
DB10
PD
VDD
DB0
DB1
DB2
DB7
DB6
DB3
DB4
DB5
12-BIT
AD5340
TOP VIEW
(Not to Scale)
DB8
DB9
DB11
LDAC
GND
BUF
VOUT
NC
VREF
CS
WR
GAIN
CLR
Figure 7. AD5340 Functional Block Diagram
Figure 8. AD5340 Pin Configuration
Table 7. AD5340 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
DB10
Parallel Data Input.
2
DB11
Most Significant Bit of Parallel Data Input.
3
BUF
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
4
VREF
Reference Input.
5
VOUT
Output of DAC. Buffered output with rail-to-rail operation.
6
NC
No Connect.
7
GND
Ground reference point for all circuitry on the part.
8
CS
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9
WR
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10
GAIN
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
11
CLR
Asynchronous active low control input that clears all input registers and DAC registers to zero.
12
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
13
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
14
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
15 to 24
DB0 to DB9
Ten Parallel Data Inputs.


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