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FDG6331L Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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FDG6331L Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 4 page FDG6331L Rev B (W) Electrical Characteristics T A = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVIN Vin Breakdown Voltage VON/OFF = 0 V, ID = –250 µA 8 V ILoad Zero Gate Voltage Drain Current VIN = –6.4 V, VON/OFF = 0 V –1 µA IFL Leakage Current, Forward VON/OFF = 0 V, VIN = 8 V 100 nA IRL Leakage Current, Reverse VON/OFF = 0 V, VIN = –8 V –100 nA On Characteristics (Note 2) VON/OFF (th) Gate Threshold Voltage VIN = VON/OFF, ID = –250 µA 0.4 0.9 1.5 V RDS(on) Static Drain–Source On–Resistance (Q2) VIN = 4.5 V, ID = –0.8 A VIN =2.5 V, ID = –0.7 A VIN = 1.8 V, ID = –0.6 A 155 193 248 260 330 450 m Ω RDS(on) Static Drain–Source On–Resistance (Q1) VIN = 4.5 V, ID = 0.4A VIN = 2.7 V, ID = 0.2 A 310 380 400 500 m Ω Drain–Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain–Source Diode Forward Current –0.25 A VSD Drain–Source Diode Forward Voltage VON/OFF = 0 V, IS = –0.25 A(Note 2) –1.2 V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDG6331L Load Switch Application Circuit Q2 Q1 R1 IN OUT ON/OFF LOAD C1 R2 External Component Recommendation: For additional in-rush current control, R2 and C1 can be added. For more information, see application note AN1030. |
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