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FDG6320C Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor

Il numero della parte FDG6320C
Spiegazioni elettronici  Dual N & P Channel Digital FET
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FDG6320C Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor

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November 1998
FDG6320C
Dual N & P Channel Digital FET
General Description
Features
Absolute Maximum Ratings T
A = 25
oC unless other wise noted
Symbol
Parameter
N-Channel
P-Channel
Units
VDSS
Drain-Source Voltage
25
-25
V
V
GSS
Gate-Source Voltage
8
-8
V
I
D
Drain Current
- Continuous
0.22
-0.14
A
- Pulsed
0.65
-0.4
P
D
Maximum Power Dissipation
(Note 1)
0.3
W
T
J,TSTG
Operating and Storage Temperature Ranger
-55 to 150
°C
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6
kV
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
415
°C/W
FDG6320C Rev. D
N-Ch 0.22 A, 25 V, R
DS(ON) = 4.0 @ VGS= 4.5 V,
R
DS(ON) = 5.0 @ VGS= 2.7 V.
P-Ch -0.14 A, -25V, R
DS(ON) = 10 @ VGS= -4.5V,
R
DS(ON) = 13 @ VGS= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (V
GS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
These dual N & P-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance.
This
device has been designed
especially for low voltage applications as a replacement for
bipolar digital transistors and small signal MOSFETS. Since
bias resistors are not required, this dual digital FET can
replace several different digital transistors, with different bias
resistor values.
SC70-6
SuperSOT
TM-6
SOIC-14
SO-8
SOT-8
SOT-23
D1
S2
G1
D2
S1
G2
SC70-6
.20
pin 1
5
3
2
4
1
6
© 1998 Fairchild Semiconductor Corporation


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