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FDG314P Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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FDG314P Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 5 page FDG314P Rev.C FDG314P Digital FET, P-Channel July 2000 2000 Fairchild Semiconductor International Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter Ratings Units VDSS Drain-Source Voltage -25 V VGSS Gate-Source Voltage ±8V ID Drain Current - Continuous (Note 1a) -0.65 A - Pulsed -1.8 Power Dissipation for Single Operation (Note 1a) 0.75 W PD (Note 1b) 0.48 TJ, Tstg Operating and Storage Junction Temperature Range -55 to +150 °C ESD Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf/1500 Ohm) 6.0 kV Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient (Note 1b) 260 °C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape Width Quantity .14 FDG314P 7’’ 8mm 3000 units General Description This P-Channel enhancement mode field effect transistor is produced using Fairchild Semiconductor’s proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on- state resistance at low gate drive conditions. This device is designed especially for battery power applications such as notebook computers and cellular phones. This device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts. Applications • Power Management • Load switch • Signal switch Features • -0.65 A, -25 V. R DS(ON) = 1.1 Ω @ VGS = -4.5 V R DS(ON) = 1.5 Ω @ VGS = -2.7 V. • Very low gate drive requirements allowing direct operation in 3V cirucuits (V GS(th) <1.5 V). • Gate-Source Zener for ESD ruggedness (>6 kV Human Body Model). • Compact industry standard SC70-6 surface mount package. SC70-6 D S D G D D 3 5 6 4 1 2 3 |
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