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CD4023BCN Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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CD4023BCN Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2000 Fairchild Semiconductor Corporation DS005956 www.fairchildsemi.com October 1987 Revised August 2000 CD4023BC Buffered Triple 3-Input NAND Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P- channel enhancement mode transistors. They have equal source and sink current capabilities and conform to stan- dard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs are protected against static dis- charge with diodes to VDD and VSS. Features s Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VDD (typ) s Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS s 5V–10V–15V parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full temperature range Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code. Connection Diagram Top View Block Diagram 1/ 3 Device Shown *All Inputs Protected by Standard CMOS Input Protection Circuit. Order Number Package Number Package Description CD4023BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow CD4023BCS M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4023BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
Codice articolo simile - CD4023BCN |
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Descrizione simile - CD4023BCN |
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