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CD4014BCM Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor

Il numero della parte CD4014BCM
Spiegazioni elettronici  8-Stage Static Shift Register
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AC Electrical Characteristics (Note 5)
TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ
Note 5: AC Parameters are guaranteed by DC correlated testing.
Note 6: If more than one unit is cascaded trCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the esti-
mated capacitive load.
Note 7: Setup times are measured with reference to clock and a fixed hold time (tH) as specified.
Note 8: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note
AN-90.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHL, tPLH
Propagation Delay Time
VDD = 5V
200
320
ns
VDD = 10V
80
160
ns
VDD = 15V
60
120
ns
tTHL, tTLH
Transition Time
VDD = 5V
100
200
ns
VDD = 10V
50
100
ns
VDD = 15V
40
80
ns
fCL
Maximum Clock
VDD = 5V
2.8
4
MHz
Input Frequency
VDD = 10V
6
12
MHz
VDD = 15V
8
16
MHz
tW
Minimum Clock
VDD = 5V
90
180
ns
Pulse Width
VDD = 10V
40
80
ns
VDD = 15V
25
50
ns
trCL, tfCL
Clock Rise and
VDD = 5V
15
µs
Fall Time (Note 6)
VDD = 10V
15
µs
VDD = 15V
15
µs
tS
Minimum Set-Up Time
VDD = 5V
60
120
ns
(Note 7) Serial Input
VDD = 10V
40
80
ns
tH ≥ 200 ns
VDD = 15V
30
60
ns
Parallel Inputs
VDD = 5V
80
160
ns
tH ≥ 200 ns
VDD = 10V
40
80
ns
VDD = 15V
30
60
ns
Parallel/Serial Control
VDD = 5V
100
200
ns
tH ≥ 200 ns
VDD = 10V
50
100
ns
VDD = 15V
40
80
ns
tH
Minimum Hold Time
VDD = 5V
0
ns
Serial In, Parallel In, tS ≥ 400 ns VDD = 10V
10
ns
Parallel/Serial Control
VDD = 15V
15
ns
CI
Average Input Capacitance
Any Input
5
7.5
pF
(Note 8)
CPD
Power Dissipation Capacitance
110
pF
(Note 8)


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