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74VCXF162835MTD Scheda tecnica(PDF) 5 Page - Fairchild Semiconductor |
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74VCXF162835MTD Scheda tecnica(HTML) 5 Page - Fairchild Semiconductor |
5 / 8 page 5 www.fairchildsemi.com AC Electrical Characteristics (Note 11) Note 11: For CL = 50pF, add approximately 300ps to the AC maximum specification. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). AC Electrical Characteristics Over Load (Note 13) Note 13: Characterized only. Dynamic Switching Characteristics Symbol Parameter TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω Units VCC = 3.3V ± 0.3V VCC = 2.5 ± 0.2V VCC = 1.8 ± 0.15V Min Max Min Max Min Max fMAX Maximum Clock Frequency 250 200 100 MHz tPHL, tPLH Propagation Delay 0.6 3.1 0.8 4.0 1.5 7.2 ns Bus to Bus tPHL, tPLH Propagation Delay 1.0 3.2 1.5 4.1 2.0 7.4 ns Clock to Bus tPHL, tPLH Propagation Delay 0.6 3.7 0.8 4.7 1.5 8.5 ns LE to Bus tPZL, tPZH Output Enable Time 0.6 4.3 0.8 5.9 1.5 9.8 ns tPLZ, tPHZ Output Disable Time 0.6 4.2 0.8 4.7 1.5 7.9 ns tS Setup Time 1.5 1.5 2.5 ns tH Hold Time 0.7 0.7 1.0 ns tW Pulse Width 1.5 1.5 4.0 ns tOSHL Output to Output Skew 0.5 0.5 0.75 ns tOSLH (Note 12) Symbol Parameter TA = −0°C to +85°C, RL = 500Ω VCC = 3.3V ± 03V Units CL = 50 pF Min Max tPHL, tPLH Prop Delay Bus to Bus 1.0 3.4 ns tPHL, tPLH Prop Delay Clock to Bus 1.4 3.5 ns tPHL, tPLH Prop Delay LE to Bus 1.0 4.0 ns tPZL, tPZH Output Enable Time 1.0 4.6 ns tPLZ, tPHZ Output Disable Time 1.0 4.5 ns tS Setup Time 1.0 ns tH Hold Time 0.6 ns Symbol Parameter Conditions VCC TA=+25°C Units (V) Typical VOLP Quiet Output Dynamic Peak VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 0.25 2.5 0.40 V 3.3 0.55 VOLV Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 −0.25 2.5 −0.40 V 3.3 −0.55 VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V 1.8 1.35 2.5 1.80 V 3.3 2.30 |
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