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74VCX16721 Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor

Il numero della parte 74VCX16721
Spiegazioni elettronici  Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74VCX16721 Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor

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March 1998
Revised April 1999
© 1999 Fairchild Semiconductor Corporation
DS500143.prf
www.fairchildsemi.com
74VCX16721
Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant
Inputs and Outputs
General Description
The VCX16721 contains twenty non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications.
The 74VCX16721 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX16721 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.8V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (CLK to On)
3.5 ns max for 3.0V to 3.6V VCC
4.4 ns max for 2.3V to 2.7V VCC
8.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V V
CC
±18 mA @ 2.3V V
CC
±6 mA @ 1.65V V
CC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model
> 2000V
Machine model
> 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
Package Number
Package Description
74VCX16721MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
Output Enable Input (Active LOW)
CLK
Clock Input
D0–D19
Inputs
O0–O19
Outputs
CE
Clock Enable Input (Active LOW)


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