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74ACTQ74SJ Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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74ACTQ74SJ Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page © 1999 Fairchild Semiconductor Corporation DS010920 www.fairchildsemi.com March 1993 Revised November 1999 74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop General Description The 74ACTQ74 is a dual D-type flip-flop with Asynchro- nous Clear and Set inputs and complementary (Q, Q) out- puts. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. The ACTQ74 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features s ICC reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s 4 kV minimum ESD immunity s TTL-compatible inputs Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. Connection Diagram Pin Descriptions FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74ACTQ74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74ACTQ74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description D1, D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs |
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