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74ACTQ16543 Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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74ACTQ16543 Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page December 1991 Revised December 1998 © 1999 Fairchild Semiconductor Corporation DS010967.prf www.fairchildsemi.com 74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs General Description The ACTQ16543 contains sixteen non-inverting transceiv- ers containing two sets of D-type registers for temporary storage of data flowing in either direction. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit inde- pendent input and output control in either direction of data flow. The ACTQ16543 utilizes Fairchild Quiet Series ™ technol- ogy to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series ™ fea- tures GTO ™ output control and undershoot corrector for superior performance. Features s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Independent registers for A and B buses s Separate controls for data flow in each direction s Back-to-back registers for storage Multiplexed real-time and stored data transfers s Separate control logic for each byte s 16-bit version of the ACTQ543 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loading specs for both 50 pF and 250pF loads Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions FACT ™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74ACTQ16543SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ACTQ16543MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Descriptions OEABn A-to-B Output Enable Input (Active LOW) OEBAn B-to-A Output Enable Input (Active LOW) CEABn A-to-B Enable Input (Active LOW) CEBAn B-to-A Enable Input (Active LOW) LEABn A-to-B Latch Enable Input (Active LOW) LEBAn B-to-A Latch Enable Input (Active LOW) A0–A15 A-to-B Data Inputs or B-to-A 3-STATE Outputs B0–B15 B-to-A Data Inputs or A-to-B 3-STATE Outputs |
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