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54VCXH162245 Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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54VCXH162245 Scheda tecnica(HTML) 1 Page - STMicroelectronics |
1 / 19 page July 2011 Doc ID 10632 Rev 9 1/19 19 54VCXH162245 Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs Features ■ 1.65 to 3.6 V inputs and outputs ■ High speed A outputs: –tPD = 3.4 ns at VCC = 3.0 to 3.6 V –tPD = 4.3 ns at VCC = 2.3 to 2.7 V ■ Symmetrical impedance A output: –|IOH| = IOL = 12 mA (Min.) at VCC = 3.0 V –|IOH| = IOL = 8 mA (Min.) at VCC = 2.3 V ■ High speed B outputs: –tPD = 2.5 ns (Max.) at VCC = 3.0 to 3.6 V –tPD = 3.2 ns (Max.) at VCC = 2.3 to 2.7 V ■ Symmetrical impedance A output: –|IOH| = IOL = 24 mA (Min.) at VCC = 3.0 V –|IOH| = IOL = 18 mA (Min.) at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ 26 Ω serie resistors in A port output ■ Operating voltage range: –VCC(Opr) = 1.65 V to 3.6 V ■ Pin and function compatible with 54 series H162245 ■ Bus hold provided on both sides ■ Cold spare function ■ Latch-up performance exceeds 300 mA (JESD 17) ■ ESD performance: – HBM > 2000 V (MIL STD 883 method 3015); MM > 200 V ■ 300 krad Mil1019.6 condition A, (RHA QML qualification extension undergone) ■ No SEL, no SEU and no SET under 110 Mev/cm2/mg LET heavy ions irradiation ■ QML qualified product ■ Device fully compliant with DSCC SMD 5962-02508 ■ 100 mV typical Input hysteresis Description The 54VCXH162245 is a low voltage CMOS 16 bit bus transceiver (3-state) fabricated with sub- micron silicon gate and five-layer metal wiring C²MOS technology. It is ideal for low power and very high speed 1.65 to 3.6 V applications; it can be interfaced to 3.6 V signal environment for both inputs and outputs. This IC is intended for two- way asynchronous communication between data buses; the direction of data transmission is determined by DIR input. The two enable inputs nG can be used to disable the device so that the buses are effectively isolated. The device circuits is including 26 Ω series resistance in the A port outputs. These resistors permit to reduce line noise in high speed applications. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2 kV ESD immunity and transient excess voltage. All floating bus terminals during high Z state must be held HIGH or LOW. Flat-48 The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package. www.st.com |
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