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AD8362-EVAL Scheda tecnica(PDF) 32 Page - Analog Devices |
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AD8362-EVAL Scheda tecnica(HTML) 32 Page - Analog Devices |
32 / 36 page AD8362 Rev. B | Page 32 of 36 AD8362 EVALUATION BOARD The AD8362 evaluation board provides for a number of different operating modes and configurations, including many of those described in this data sheet. The measurement mode is set up by positioning SW2 as shown in Figure 69. The AD8362 can be operated in controller mode by flipping SW2 to its alternate position, thereby connecting the VSET pin to the VSET connector and applying the setpoint voltage to the VSET connector. The internal voltage reference is used for the target voltage when SW1 is in the position shown in Figure 69. This voltage may optionally be reduced via a voltage divider implemented with R4 and R5, with LK1 in place as shown in Figure 69 and SW1 switched to its alternate position. Alternatively, an external target voltage may be used with SW1 switched to its alternate position, LK1 removed, and the external target voltage applied to the VTGT connector. In measurement mode, the slope of the response at VOUT may be increased through the use of a voltage divider implemented with the appropriately valued resistors, as explained in this data sheet, in Positions R17 and R9, and with SW2 switched to its alternate position. The AD8362 is powered up with SW3 in the position shown in Figure 69 and connector PWDN open. The part can be powered down either by connecting a logic high voltage to connector PWDN with SW3 in the position shown in Figure 69 or by switching SW3 to its alternate position. Balun Transformer T1 may be removed and replaced by two capacitors and an inductor, as shown in Figure 54, or by two 0 Ω resistors (links, size 0402): one in series with Capacitors C6 and C10, and the other in series with C5 and a 100 Ω resistor installed in Position R16, to implement the circuit shown in Figure 53. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 COMM CHPF DECL INHI INLO DECL PWDN COMM ACOM VREF VTGT VPOS VOUT VSET ACOM CLPF AD8362 C6 100pF C5 100pF C7 1000pF C4 1000pF R15 0 Ω R14 OPEN C8 1000pF SW3 R16 OPEN C10 1000pF RFIN PDWN R13 10k Ω R17 OPEN SW2 C3 0.1 µF C9 OPEN R9 10k Ω R5 10k Ω R4 0 Ω R6 0 Ω R7 0 Ω LK1 VREF VTGT VOUT VSET SW1 R10 0 Ω R8 0 Ω VPOS R1 0 Ω C2 100pF C1 0.1 µF AGND T1 Figure 69. Evaluation Board Schematic |
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