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ADMC401-PB Scheda tecnica(PDF) 4 Page - Analog Devices |
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ADMC401-PB Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 60 page REV. B ADMC401 –4– ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . . . –40 °C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65 °C to +150°C Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280 °C *Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stresses only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC401 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Temperature Instruction Package Package Model Range Rate Description Option ADMC401BST –40 °C to +85°C 26 MHz 144-Lead Plastic Thin Quad Flatpack (LQFP) ST-144 ADMC401-ADVEVALKIT Development Tool Kit ADMC401-PB Evaluation/Processor Board Timing Parameters GENERAL NOTES Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times. TIMING NOTES Switching characteristics specify how the processor changes its signals. You have no control over this timing; it is dependent on the internal design. Timing requirements apply to signals that are controlled outside the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with another device. Switching characteristics tell you what the device will do under a given circumstance. Also, use the switching characteristics to ensure any timing requirement of a device connected to the processor (such as memory) is satisfied. MEMORY REQUIREMENTS This chart links common memory device specification names and ADMC401 timing parameters for your convenience. Common Parameter Memory Device Name Function Specification Name tASW A0–A13, DMS, PMS Address Setup to Setup before WR Low Write Start tAW A0–A13, DMS, PMS Address Setup to before WR Deasserted Write End tWRA A0–A13, DMS, PMS Address Hold Time Hold after WR Deasserted tDW Data Setup before WR High Data Setup Time tDH Data Hold after WR High Data Hold Time tRDD RD Low to Data Valid OE to Data Valid tAA A0–A13, DMS, PMS, Address Access Time BMS to Data Valid |
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