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AD9101SE Scheda tecnica(PDF) 5 Page - Analog Devices |
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AD9101SE Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 12 page AD9101 –5– REV. 0 V OUT TS ACQUISITION TIME AT HC TO X% V OUT TRACK HOLD TRACK-TO-HOLD INDUCED GLITCH V HC t DHT 1.5ns V HC AMP HC SAMPLER Figure 1. Acquisition Time at Hold Capacitor during the track time. However, since the output amplifier al- ways “tracks” the front end circuitry, it “catches up” and di- rectly superimposes itself (less about 500 ps of analog delay) to VHC. Since the small signal settling time of the output amplifier can be about 1.2 ns to ±1 mV, and is significantly less than the hold time, acquisition time should be referenced to the hold capacitor. Most of the hold settling time and output acquisition time are due to the sampler and the switch network. (Output acquisition time is as seen on a scope at the output. This is typically 1.7 ns longer than actual acquisition time.) For track time, the output amplifier contributes only about 5 ns of the total; in hold mode, it contributes 1.7 ns (as stated above). A stricter definition of acquisition would actually include both the acquisition and track-to-hold settling times to a defined ac- curacy. To obtain 12-bit+ distortion levels and 50 MSPS opera- tion, the minimum recommended track and hold times are 12 ns and 8 ns, respectively. To drive an 8-bit flash converter (such as the AD9002) with a 2 V p-p full-scale input, hold time to 1 LSB accuracy will be limited primarily by the aperture time of the encoder, rather than by the AD9101. This makes it pos- sible to reduce track time to as little as 5 ns, with hold time cho- sen to optimize the encoder’s performance. Though acquisition time and track-to-hold settling time to 1/2 LSB (0.4%) accuracy are 6 ns and 4 ns respectively, it is still possible to achieve –45 dB SNR performance at clock speeds to 125 MSPS. This is because the settling error is roughly propor- tional to the signal level and is partially cancelled due to the high phase margin of the input sampler. Hold vs. Track Mode Distortion In many traditional high speed, open-loop track-and-holds, track mode distortion is often much better than hold mode dis- tortion. Track mode distortion does not include nonlinearities due to the switch network, and does not correlate to the relevant hold mode distortion. But since hold mode distortion has tradi- tionally been omitted from manufacturer’s specification tables, users have had to discover for themselves the effective overall hold mode distortion of the combined T/H and encoder. THEORY OF OPERATION The AD9101 employs a new and unique track-and-hold archi- tecture. Previous commercially available high speed track-and- holds used an open loop input buffer, followed by a diode bridge, hold capacitor, and output buffer (closed or open loop) with a FET device usually connected to the hold capacitor. This architecture required mixed device technology and, usually, hy- brid construction. The sampling rate of these hybrids has been limited to 20 MSPS for 12-bit accuracy. Distortion generated in the front-end amplifier/bridge limited the dynamic range perfor- mance to the “mid –70 dBFS” for analog input signals of less than 10 MHz. Broadband and switch-generated noise limited the SNR of previous track-and-holds to about 70 dB. The AD9101 is a monolithic device using a high frequency complementary bipolar process to achieve new levels of high speed precision. Its architecture completely breaks from the tra- ditional architecture described above. The hold switch has been integrated into the first stage closed-loop buffer. This innova- tion provides error (distortion) correction for both the switch and buffer while still achieving slew rates representative of an open-loop design. In addition, acquisition slew current for the hold capacitor is higher than the traditional diode bridge switch configurations, removing a main contributor to the limits of maximum sampling rate, input frequency, and distortion. The closed-loop output amplifier includes zero voltage bias cur- rent cancellation, which results in high-temperature droop rates close to those found in FET type inputs. This closed-loop am- plifier inherently provides high speed loop correction and has extremely low distortion even when heavily loaded. Extremely fast time constant linearity (7 ns to 0.01% for a 4 V output step) ensures that the output amplifier does not limit the AD9101 sampling rate or analog input frequency. (The acquisi- tion and settling time are primarily limited only by the input sampler.) The output is transparent to the overall AD9101 hold mode distortion levels for loads as low as 50 Ω. Full-scale track and acquisition slew rates achieved by the AD9101 are 1800 V/ µs and 1700 V/µs, respectively. When com- bined with excellent phase margin (typically 5% overshoot), wide bandwidth, and dc gain accuracy, acquisition time to 0.01% is only 11 ns. Acquisition Time Acquisition time is the amount of time it takes the AD9101 to reacquire the analog input when switching from hold-to-track mode. The interval starts at the 50% clock transition point and ends when the input signal is reacquired to within a specified er- ror band at the hold capacitor. The hold-to-track switch delay (tDHT) cannot be subtracted from this acquisition time for 12-bit performance because it is a charging time and analog output delay that occurs when moving from hold to track; this delay is typically 1.5 ns. Therefore, the track time required for the AD9101 is the acquisition time which includes tDHT. Note that the acquisition time is defined as the settled voltage at the hold capacitor and does not include the delay and settling time of the output amplifier. The example in Figure 1 illustrates why the output amplifier does not contribute to the overall acquisition time. The exaggerated illustration in Figure 1 shows that VHC has settled to within x% of its final value, but VOUT (due to slew rate limitations, finite BW, power supply ringing, etc.) has not settled |
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