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AD9059 Scheda tecnica(PDF) 9 Page - Analog Devices |
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AD9059 Scheda tecnica(HTML) 9 Page - Analog Devices |
9 / 12 page AD9059 –9– REV. 0 +VD ENCODE PWRDN D0–D7 +VDD +3V TO +5V 500 Ω +VD VREF AIN Digital Inputs Analog Inputs Digital Outputs 800 Ω +VD VREF 3k Ω 2.5k Ω +2.5V Voltage Reference Figure 18. Equivalent Circuits Evaluation Board The AD9059/PCB evaluation board provides an easy-to-use analog/digital interface for the dual 8-bit, 60 MSPS ADC. The board includes typical hardware configurations for a variety of high speed digitization evaluations. On-board components in- clude the AD9059 (in the 28-pin SSOP package), optional ana- log input buffer amplifiers, digital output latches, board timing drivers, and configurable jumpers for ac coupling, dc coupling, and power-down function testing. The board is configured at shipment for dc coupling using the AD9059’s internal reference. For dc coupled analog input applications, amplifiers U3 and U4 are configured to operate as unity gain inverters with adjustable offset for the analog input signals. For full-scale ADC drive each analog input signal should be 1 V p-p into 50 Ω referenced to ground. Each amplifier offsets its analog signal by +VREF (+2.5 V typical) to center the voltage for proper ADC input drive. For dc coupled operation, connect E7 to E9 (analog in- put A to R11), E14 to E13 (amplifier output to analog input A of AD9059), E4 to E5 (analog input B to R10), and E11 to E10 (amplifier output to analog input B of AD9059) using the board jumper connectors. For ac coupled analog input applications, amplifiers U3 and U4 are removed from the analog signal paths. The analog signals are coupled through capacitors C11 and C12, each terminated to the VREF voltage through separate 1 k Ω resistors (providing bias current for the AD9059 analog inputs, AINA and AINB). Analog input signals to the board should be 1 V p-p into 50 Ω for full-scale ADC drive. For ac coupled operation, connect E7 to E8 (analog input A to C12 feedthrough capacitor), E13 to E15 (C12 to R15 termination resistor for channel A), E4 to E6 (analog input B to C11 feedthrough capacitor), and E10 to E12 (C11 to R14 termination resistor for channel B) using the board jumper connectors. The on-board reference voltage may be used to drive the ADC or an external reference may be applied. The standard configu- ration employs the internal voltage reference without any exter- nal connection requirements. An external voltage reference may be applied at board connector input REF to overdrive the lim- ited current output of the AD9059’s internal voltage reference. The external voltage reference should be +2.5 V typical. The power-down function of the AD9059 can be exercised through a board jumper connection. Connect E2 to E1 (+5 V to PWRDN) for power-down mode operation. For normal op- eration, connect E3 to E1 (ground to PWRDN). The encode signal source should be TTL/CMOS compatible and capable of driving a 50 Ω termination. The digital outputs of the AD9059 are buffered through latches on the evaluation board (U5 and U6) and are available for the user at connector Pins 30–37 and Pins 22–29. Latch timing is derived from the ADC ENCODE clock and a digital clocking signal is provided for the board user at connector Pins 2 and 21. |
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