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AD8842 Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD8842 Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 12 page REV. 0 –4– AD8842 PIN DESCRIPTION Pin Mnemonic Description 1VOUTC DAC C Output 2VOUTB DAC B Output 3VOUTA DAC A Output 4VINB DAC B Reference Input 5VINA DAC A Reference Input 6 GND Ground 7 PR Preset Input, active low, all DAC registers = 80H 8VINE DAC E Reference Input 9VINF DAC F Reference Input 10 VOUTE DAC E Output 11 VOUTF DAC F Output 12 VOUTG DAC G Output 13 VOUTH DAC H Output 14 VING DAC G Reference Input 15 VINH DAC H Reference Input 16 LD Load DAC Register Strobe, active- high input that transfers the data bits from the serial-input register into the decoded DAC register. SDI and CLK inputs are disabled when LD is high. See Tables I and II 17 CLK Serial Clock Input, positive edge triggered 18 SDO Serial Data Output, active totem pole output 19 VSS Negative 5 V Power Supply 20 SDI Serial Data Input 21 VDD Positive 5 V Power Supply 22 VIND DAC D Reference Input 23 VINC DAC C Reference Input 24 VOUTD DAC D Output PIN CONFIGURATION VOUTC VOUTB VOUTD VINC VINB GND PR SDI VSS SDO VOUTA VINA VIND VDD VINE CLK VINF LD VOUTE VINH VOUTF VING VOUTG VINH 14 1 2 24 23 5 6 7 20 19 18 3 4 22 21 817 916 10 15 11 TOP VIEW (Not to Scale) 11 12 13 AD8842 |
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