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AD7118UQ2 Scheda tecnica(PDF) 4 Page - Analog Devices

Il numero della parte AD7118UQ2
Spiegazioni elettronici  LOGDAC CMOS Logarithmic D/A Converter
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7118
REV. A
–4–
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
The AD7118 consists of a 17-bit R-2R CMOS multiplying D/A
converter with extensive digital input logic. The logic translates
the 6-bit binary input into a 17-bit word which is used to drive
the D/A converter. Table I gives the nominal output voltages
(and levels relative to 0 dB = 10 V) for all possible input codes.
The transfer function for the circuit of Figure 1 is given by:
VO =−V IN10exp−
1.5N
20
or
VO
V IN
dB
=−1.5N
where N is the binary input for values 0 to 57. For 60
≤ N ≤ 63
the output is zero. See note 3 at bottom of Table I.
Figure 1. Typical Circuit Configuration
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows a simplified circuit of the D/A converter section
of the AD7118 and Figure 3 gives an approximate equivalent
circuit.
The current source ILEAKAGE is composed of surface and junc-
tion leakages and as with most semiconductor devices, roughly
doubles every 10
°C–see Figure 10. The resistor R
O as shown in
Figure 3 is the equivalent output resistance of the device which
varies with input code (excluding all 0’s code) from 0.8R to
2R. R is typically 12 k
Ω. C
OUT is the capacitance due to the
N-channel switches and varies from about 50 pF to 80 pF de-
pending upon the digital input. For further information on
CMOS multiplying D/A converters refer to “Application Guide
to CMOS Multiplying D/A Converters” which is available from
Analog Devices, Publication Number G479–15–8/78.
Figure 2. Simplified D/A Circuit of AD7118
Figure 3. Equivalent Analog Output Circuit of AD7118
Digital Input
Attenuation
ND5
D0
dB
VOUT
1
N
Digital Input
Attenuation
VOUT
1
00
00 00 00
00.0
10.00
31
01 11 11
46.5
0.0473
01
00 00 01
01.5
8.414
32
10 00 00
48.0
0.0398
02
00 00 10
03.0
7.079
33
10 00 01
49.5
0.0335
03
00 00 11
04.5
5.957
34
10 00 10
51.0
0.0282
04
00 01 00
06.0
5.012
35
10 00 11
52.5
0.0237
05
00 01 01
07.5
4.217
36
10 01 00
54.0
0.0200
06
00 01 10
09.0
3.548
37
10 01 01
55.5
0.0168
07
00 01 11
10.5
2.985
38
10 01 10
57.0
0.0141
08
00 10 00
12.0
2.512
39
10 01 11
58.5
0.0119
09
00 10 01
13.5
2.113
40
10 10 00
60.0
0.0100
10
00 10 10
15.0
1.778
41
10 10 01
61.5
0.00841
11
00 10 11
16.5
1.496
42
10 10 10
63.0
0.00708
12
00 11 00
18.0
1.259
43
10 10 11
64.5
0.00596
13
00 11 01
19.5
1.059
44
10 11 00
66.0
0.00501
14
00 11 10
21.0
0.891
45
10 11 01
67.5
0.00422
15
00 11 11
22.5
0.750
46
10 11 10
69.0
0.00355
16
01 00 00
24.0
0.631
47
10 11 11
70.5
0.00299
17
01 00 01
25.5
0.531
48
11 00 00
72.0
0.00251
18
01 00 10
27.0
0.447
49
11 00 01
73.5
0.00211
19
01 00 11
28.5
0.376
50
11 00 10
75.0
0.00178
20
01 01 00
30.0
0.316
51
11 00 11
76.5
0.00150
21
01 01 01
31.5
0.266
52
11 01 00
78.0
0.00126
22
01 01 10
33.0
0.224
53
11 01 01
79.5
0.00106
23
01 01 11
34.5
0.188
54
11 01 10
81.0
0.000891
24
01 10 00
36.0
0.158
55
11 01 11
82.5
0.000750
25
01 10 01
37.5
0.133
56
11 10 00
84.0
0.000631
26
01 10 10
39.0
0.112
57
11 10 01
85.5
0.000531
27
01 10 11
40.5
0.0944
58
11 10 10
87.0
0.000447
28
01 11 00
42.0
0.0794
59
11 10 11
88.5
0.000376
29
01 11 01
43.5
0.0668
60
11 11 XX2
30
01 11 10
45.0
0.0562
NOTES
1V
IN = –10 V dc
2X = 1 or 0. Output is fully muted for N
≥ 60
3Monotonic operation is not guaranteed for N = 58, 59
Table I. Ideal Attenuation vs. Input Code


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