Motore di ricerca datesheet componenti elettronici |
|
AD561K Scheda tecnica(PDF) 6 Page - Analog Devices |
|
AD561K Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 8 page AD561 –6– REV. A ratio such that it is unnecessary to use additional area for ladder resistors. The current in Q16 is added to the ladder to balance it properly, but is not switched to the output; thus, full scale is 1023/1024 2 mA. The switching cell of Q3, Q4, Q5 and Q6 serves to steer the cell current either to ground (BIT 1 low) or to the DAC output (BIT 1 high). The entire switching cell carries the same current whether the bit is on or off, minimizing thermal transients and ground current errors. The logic threshold, which is generated from the positive supply (see Digital Logic Interface), is applied to one side of each cell. Figure 6. Digital Threshold vs. Positive Supply DIGITAL LOGIC INTERFACE All standard positive supply logic families interface easily with the AD561. The digital code is positive true binary (all bits high, Logic “1,” gives positive full scale output). The logic input load factor (100 nA max at Logic “1,” –25 µA max at Logic “0,” 3 pF capacitance), is less than one equivalent digital load for all logic families, including unbuffered CMOS. The digital threshold is set internally as a function of the positive supply, as shown in Figure 6. For most applications, connecting VCC to the positive logic supply will set the threshold at the proper level for maximum noise immunity. For nonstandard applications, refer to Figure 6 for threshold levels. Uncommitted bit input lines will assume a “1” state (similar to TTL), but they are high impedance and subject to noise pickup. Unused digital inputs should be directly connected to ground or VCC, as desired. SETTLING TIME The high speed NPN current steering switching cell and internally compensated reference amplifier of the AD561 are specifically designed for fast settling operation. The typical settling time to ±0.05% (1/2 LSB) for the worst case transition (major carry, 0111111111 to 1000000000) is less than 250 ns; the lower order bits all settle in less than 200 ns. (Worst case settling occurs when all bits are switched, especially the MSB.) Full realization of this high speed performance requires strict attention to detail by the user in all areas of application and testing. The settling time for the AD561 is specified in terms of the current output, an inherently high speed DAC operating mode. However, most DAC applications require a current-to-voltage conversion at some point in the signal path, although an unbuffered voltage level (not using an op amp) is suitable for use in a successive-approximation A/D converter (see page 8), or in many display applications. This form of conversion can give very fast operation if proper design and layout is done. The fastest voltage conversion is achieved by connecting a low value resistor directly to the output, as shown in Figure 9. In this case, the settling time is primarily determined by the cell switching time and by the RC time constant of the AD561 output capaci- tance of 25 picofarads (plus stray capacitance) combined with the output resistor value. Settling to 0.05% of full scale (for a full- scale transition) requires 7.6 time constants. This effect is important for R > 1 k Ω. If an op amp must be used to provide a low impedance output signal, some loss in settling time will be seen due to op amp dynamics. The normal current-to-voltage converter op amp circuits are shown in the applications circuits on page 5, using the fast settling AD509. The circuits shown settle to ±1/2 LSB in 600 ns unipolar and 1.1 µs bipolar. The DAC output capacitance, which acts as a stray capacitance at the op amp inverting input, must be compensated by a feedback capacitor, as shown. The value should be carefully chosen for each application and each op amp type. Figure 5. Circuit Diagram Showing Reference, Control Amplifier, Switching Cell, R-2R Ladder, and Bit Arrangement of AD561 |
Codice articolo simile - AD561K |
|
Descrizione simile - AD561K |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |